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PCF8531U2DA Datasheet(PDF) 22 Page - NXP Semiconductors |
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PCF8531U2DA Datasheet(HTML) 22 Page - NXP Semiconductors |
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22 / 51 page ![]() PCF8531 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 6 — 16 May 2011 22 of 51 NXP Semiconductors PCF8531 34 x 128 pixel matrix driver 9.7 Set bias system The bias voltage levels are set in the ratio of R − R − n × R − R − R (see Figure 11). Different multiplex rates require different bias settings. Bias settings are programmed by BS[2:0], which sets the binary number n. The optimum value for n is given by: Supported values of n are given in Table 8. Table 9 shows the intermediate bias voltages. Fig 11. Voltage divider chain Table 8. Programming the required bias system BS[2:0] n Bias system Comment 000 7 1 ⁄ 11 - 001 6 1 ⁄ 10 - 010 5 1 ⁄ 9 - 011 4 1 ⁄ 8 - 100 3 1 ⁄ 7 recommended for 1:34 101 2 1 ⁄ 6 recommended for 1:26 110 1 1 ⁄ 5 recommended for 1:17 111 0 1 ⁄ 4 recommended for icon mode R R R n × R R V6 = VSS V5 V4 V3 V2 V1 = VLCD 013aaa183 nmuxrate 3 – = |
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