ADIS16210

Rev. A | Page 7 of 20

BASIC OPERATION

The ADIS16210 is an autonomous system that requires no user

initialization. Upon receiving a valid power supply, it initializes

itself and starts sampling, processing, and loading data into the

output registers. When using the factory default configuration,

DIO1 provides a data ready signal. The SPI interface enables

simple integration with many embedded processor platforms,

as shown in Figure 5 (electrical connection) and Table 6 (processor

pin descriptions).

SYSTEM

PROCESSOR

SPI MASTER

ADIS16210

SCLK

CS

DIN

DOUT

SCLK

SS

MOSI

MISO

3.3V

IRQ

DIO1

VDD

I/O LINES ARE COMPATIBLE WITH

3.3V OR 5V LOGIC LEVELS

14

13

11

12

15

1

2

3

4

5

8

Figure 5. Electrical Connection Diagram

Table 6. Generic Master Processor Pin Names and Functions

Pin Name

Function

SS

Slave select

IRQ

Interrupt request, optional

MOSI

Master output, slave input

MISO

Master input, slave output

SCLK

Serial clock

The ADIS16210 SPI interface supports full duplex serial commu-

nication (simultaneous transmit and receive) and uses the bit

sequence shown in Figure 9. Table 7 provides a list of the most

common settings that initialize the serial port of a processor for the

ADIS16210 SPI interface.

Table 7. Generic Master Processor SPI Settings

Processor Setting

Description

Master

ADIS16210 operates as a slave

SCLK Rate ≤ 830 kHz

Maximum serial clock rate

SPI Mode 3

CPOL = 1 (polarity), CPHA = 1 (phase)

MSB-First Mode

Bit sequence

16-Bit Mode

Shift register/data length

READING SENSOR DATA

A single register read requires two 16-bit SPI cycles. The first

cycle requests the contents of a register using the bit assignments

in Figure 9. The register contents then follow on DOUT, during

the second sequence.

Figure 6 includes three single register reads in succession. In

this example, the process starts with DIN = 0x0400 to request

the contents of the XACCL_OUT register, followed by 0x0600

to request the contents of the YACCL_OUT register, and then

0x0800 to request the contents of the ZACCL_OUT register.

Full duplex operation enables processors to use the same 16-bit

SPI cycle to read data from DOUT while requesting the next set

of data on DIN.

DIN

DOUT

0x0400

0x0600

0x0800

XACCL_OUT

YACCL_OUT

ZACCL

_OUT

Figure 6. SPI Read Example Remove

Figure 7 provides an example of four SPI signals when reading

PROD_ID in a repeating pattern.

DOUT = 0011 1111 0101 1100 = 0x3F52 = 16210

DIN = 0101 0110 0000 0000 = 0x5600

CS

SCLK

DIN

DOUT

Figure 7. SPI Read Example, Second 16-Bit Sequence

DEVICE CONFIGURATION

The user register map (Table 8) provides a variety of control

registers, which enable optimization for specific applications.

The SPI provides access to these registers, one byte at a time,

using the bit assignments shown in Figure 9. Each register has

16 bits, where Bits[7:0] represent the lower address and Bits[15:8]

represent the upper address. Figure 8 displays the SPI signal

pattern for writing 0x07 to Address 0x38, which sets the number

of averages to 128 and the sample rate to 4 SPS.

DIN = 1011 1000 0000 0111 = 0xB807, SET AVG_CNT[7:0] = 0x07

CS

SCLK

DIN

Figure 8. Example SPI Write Pattern

R/W

R/W

A6

A5

A4

A3

A2

A1

A0

DC7

DC6

DC5

DC4

DC3

DC2

DC1

DC0

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

CS

SCLK

DIN

DOUT

A6

A5

D13

D14

D15

NOTES

1. DOUT BITS ARE PRODUCED ONLY WHEN THE PREVIOUS 16-BIT DIN SEQUENCE STARTS WITH R/W = 0.

2. WHEN CS IS HIGH, DOUT IS IN A THREE-STATE, HIGH IMPEDANCE MODE, WHICH ALLOWS MULTIFUNCTIONAL USE OF THE LINE

FOR OTHER DEVICES.

Figure 9. SPI Communication Bit Sequence