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ADN4605

Rev. 0 | Page 33 of 56

I2C SERIAL CONTROL INTERFACE

The ADN4605 register set is controlled through a 2-wire I2C

interface. To access the I2C serial interface, both the SER/PAR

line and I2C/SPI lines must be held at logic high. The ADN4605

acts only as an I2C slave device. Therefore, the I2C bus in the

system needs to include an I2C master to configure the

and other I2C devices that may be on the bus.

ADN4605

The ADN4605 I2C interface can be run in the standard

(100 kHz) and fast (400 kHz) modes. The SDA line only

changes value when the SCL pin is low with two exceptions.

To indicate the beginning or continuation of a transfer, the

SDA pin is driven low while the SCL pin is high; to indicate

the end of a transfer, the SDA line is driven high while the

SCL line is high. Therefore, it is important to control the

SCL clock to toggle only when the SDA line is stable unless

indicating a start, repeated start, or stop condition. To establish

I2C communication with the ADN4605, parallel address lines

(ADDR[7:1]) need to be configured to the user-assigned I2C

device address as shown in Table 17.

Table 17. Example of I2C Device Address Assignment

I2C Device Address

0x90

0x92

0x94

0x96

I2C DATA WRITE

To write data to the ADN4605 register set, a microcontroller, or

any other I2C master, must send the appropriate control signals

to the ADN4605 slave device. The steps to be followed are listed

below; the signals are controlled by the I2C master unless other-

wise specified. A diagram of the procedure is shown in Figure 46.

Send a start condition (while holding the SCL line high,

pull the SDA line low).

Send the ADN4605 part address (seven bits) whose bits are

controlled by the input pins ADDR[7:1]. This transfer

should be MSB first.

Send the write indicator bit (0).

Wait for the ADN4605 to acknowledge the request.

Send the register address (eight bits) to which data is to be

written. This transfer should be MSB first.

Wait for the ADN4605 to acknowledge the request.

Send the data (eight bits) to be written to the register

whose address was set in Step 5. This transfer should be

MSB first.

Wait for the ADN4605 to acknowledge the request.

Do one or more of the following:

Send a stop condition (while holding the SCL line high,

pull the SDA line high) and release control of the bus.

Send a repeated start condition (while holding the

SCL line high, pull the SDA line low) and continue

with Step 2 of the write procedure (see the I2C Data

Write section) to perform a write.

Send a repeated start condition (while holding the

SCL line high, pull the SDA line low) and continue

with Step 2 of this procedure to perform a read from

another address.

Send a repeated start condition (while holding the

SCL line high, pull the SDA line low) and continue

with Step 8 of this procedure to perform a read from

the same address.

The ADN4605 write process is shown in Figure 46. The SCL

signal is shown along with a general write operation and a

specific example. In the example, Data 0x4B is written to

Address 0x6D of an ADN4605 part with a part address of 0x92.

The ADN4605 device address selections are more flexible than

shown. It is important to note that the SDA line only changes

when the SCL line is low, except for the case of sending a start,

stop, or repeated start condition, Step 1 and Step 9 in this case.

START

R/W ACK

ACK

STOP

DATA

ADDR

[1:0]

b10010

SCL

SDA

EXAMPLE

Figure 46. I2C Write Diagram

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