TLE5011 datasheet(25/45 Pages) INFINEON

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TLE5011

Specification

Final Data Sheet

V2.0, 2011-03

The margin time shown in Table 14 is the time between write access to the SSC data line and the earliest possible

sample read of the TLE5011 itself for read-back.

It is useful to have a maximum distance between the WRITE and subsequent READ. This ensures a reliable read-

back of the written data for the Slave-Active Byte generation.

3.9.2

SSC Baud rate

The SSC baud rate depends on the internal clock frequency.

Twelve internal digital clock cycles are necessary to ensure reliable operation. Therefore, the maximum SSC baud

rate depends on the external CLK.

3.9.3

SSC Spike Filter

A spike filter for all SSC lines can be selected via the SSC_FILT bit.

SSC Spike Filter Off

When the spike filter is disabled, each slope with rising voltage is used to define a bit. This is independent of the

length of the sampled pulse. For example, a positive spike generates a rising and a falling edge.

SSC Spike Filter On

A sliding window with four consecutive sample bits is analyzed.

The sample frequency is:

Rising Edge Detect for SCK

•

After a rising edge (LH combination), at least one of the two following samples must be high. Valid bit

combinations: 0111 , 0110 , 0101.

•

A falling condition must be detected previously.

Falling Edge Detect for SCK

•

After a falling edge (HL combination), at least one of the two following samples must be low. Valid bit

combinations: 1000 , 1001 , 1010.

•

A rising condition must be detected previously.

Table 14

Maximum Pull-up Time Margin with Worst-Case Specified Timing

SSC_FILT

SSC_TIMING

Min. t

PU Margin

1) Calculation: Margin=t

SCKl(min)+tDATwMAX-(tPU)-tDATrMIN.For Margin<50 ns no problems can occur.

Unit

Comment

don’t care

150

SSC

CLK

-----------

DIGIT

---------------

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