DAC3482 datasheet(9/79 Pages) TI1

9 / 79 page

DAC3482

www.ti.com

SLAS748A

– MARCH 2011 – REVISED JUNE 2011

ELECTRICAL CHARACTERISTICS

– DIGITAL SPECIFICATIONS

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LVDS INPUTS: D[15:0]P/N, DATACLKP/N, FRAMEP/N, SYNCP/N, PARITYP/N(1)

Logic high differential

VA,B+

200

400

1000

input voltage threshold

Logic low differential

VA,B–

–200

input voltage threshold

VCOM

Input common mode

1.075

1.2

Internal termination

110

LVDS Input capacitance

Interleaved LVDS data

fINTERL

1250

MSPS

transfer rate

Word-wide interface mode

625

fDATA

Input data rate

MSPS

Byte-wide interface mode

312.5

CLOCK INPUT (DACCLKP/N)

Duty cycle

40%

60%

Differential voltage(2)

0.4

1.0

DACCLKP/N input

1250

MHz

frequency

OUTPUT STROBE (OSTRP/N)

fOSTR = fDACCLK / (n x 8 x Interp) where n is any positive integer,

fDACCLK /

fOSTR

Frequency

MHz

fDACCLK is DACCLK frequency in MHz

(8 x interp)

Duty cycle

50%

Differential voltage

0.4

1.0

CMOS INTERFACE: ALARM, SDO, SDIO, SCLK, SDENB, SLEEP, RESETB, TXENABLE

VIH

High-level input voltage

VIL

Low-level input voltage

0.8

IIH

High-level input current

-40

µA

IIL

Low-level input current

-40

µA

CMOS input capacitance

Iload = –100 μA

IOVDD

– 0.2

VOH

ALARM, SDO, SDIO

Iload = –2 mA

0.8 x IOVDD

Iload = 100 μA

0.2

VOL

ALARM, SDO, SDIO

Iload = 2 mA

0.5

(1)

See LVDS INPUTS section for terminology.

(2)

Driving the clock input with a differential voltage lower than 1 V may result in degraded performance.

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