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PIC24F04KA201 Datasheet(PDF) 3 Page - Microchip Technology |
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PIC24F04KA201 Datasheet(HTML) 3 Page - Microchip Technology |
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3 / 8 page ![]() 2011 Microchip Technology Inc. DS80474B-page 3 PIC24F04KA201 FAMILY Silicon Errata Issues 1. Module: Resets (BOR) A device Reset may occur if the BOR is disabled and immediately re-enabled in software (RCON<14> is cleared, and then immediately set). Work around It is recommended that several NOP instructions be added to a BOR disable/enable sequence. Alternatively, place several instructions or a short routine between the instructions to disable and enable the BOR. Affected Silicon Revisions 2. Module: Core (Deep Sleep) Deep Sleep wake-up sources may be ignored if they occur just prior to entry into Deep Sleep mode. As a result, the device may enter Deep Sleep mode when it should not. Work around If possible, configure external Deep Sleep wake-up sources to repeat themselves once. If the device does enter Deep Sleep, the second occurrence of the wake-up source will wake the device. Alternatively, synchronize the entry into Deep Sleep with external wake-up sources, where possible. Affected Silicon Revisions 3. Module: Comparator The maximum value for the input offset voltage (specification D300, VIOFF), shown in Table 26-12 of the Device Data Sheet, has changed for this silicon revision. The new value is shown in Table 3 (changes in bold). Work around None. Affected Silicon Revisions TABLE 3: COMPARATOR DC SPECIFICATIONS (PARTIAL) Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision (A1). A1 X A1 X A1 X Param No. Symbol Characteristics Min Typ Max Units Comments VIOFF Input Offset Voltage — 20 60 mV |
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