PIC24F04KA201 datasheet(5/8 Pages) MICROCHIP

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 2011 Microchip Technology Inc.

DS80474B-page 5

PIC24F04KA201 FAMILY

Module: Core (Doze Mode)

Operations that immediately follow any manipu-

lations of the DOZE<2:0> or DOZEN bits

(CLDIV<14:11>) may not execute properly. In

particular, for instructions that operate on an

SFR, data may not be read properly. Also, bits

automatically cleared in hardware may not be

cleared if the operation occurs during this

interval.

Work around

Always insert a NOP instruction before and after

either of the following:

•

Enabling or disabling Doze mode by setting

or clearing the DOZEN bit

•

Before or after changing the DOZE<2:0> bits

Affected Silicon Revisions

Data Sheet Clarifications

The following typographic corrections and clarifications

are to be noted for the latest version of the Device Data

Sheet (DS39937B):

Module: Electrical Specifications

(DC Specifications)

Table 26-5 (“BOR Trip Points”) has changed to

reflect the functionality of the LPBOR trip point

(BORV<1:0> = 00), and to make other typo-

graphic

corrections.

The

minimum

and

maximum values for the BOR trip points in

Table 26-5 have changed. The new version of

the table is shown below (changes in bold).

TABLE 26-5:

BOR TRIP POINTS

Note:

Corrections are shown in bold. Where

possible, the original bold text formatting

has been removed for clarity.

Standard Operating Conditions (unless otherwise stated)

Operating temperature

-40°C

 TA  +85°C for industrial

Param

No.

Sym

Characteristic

Min

Typ

Max

Units

Conditions

DC19

BOR Voltage on

VDD Transition

BORV = 00

—

Note (1)

BORV = 01

2.92

3.25

BORV = 10

2.63

2.7

2.92

BORV = 11

1.75

1.82 2.01

Note 1:

LPBOR re-arms the POR circuit, but does not cause a BOR.

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