PCA9621 datasheet(7/18 Pages) NXP

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PCA9621

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Product data sheet

Rev. 1 — 9 March 2011

7 of 18

NXP Semiconductors

PCA9621

65 mA 8-bit 2-wire bus output port

10. Characteristics

Table 4.

Characteristics

Tamb = −40 °C to +85 °C; voltages are specified with respect to ground (VSS); VDD = 5.5 V unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Power supply

VDD

supply voltage

operating

2.7

5.5

IDD

supply current

quiescent; VI (RESET pin) = 0 V;

VDD =5.5 V

μA

I2C-bus ports (SCL, SDA)

VI2C-bus

I2C-bus voltage

SDA, SCL

VSS − 0.3

VDD +0.3

VIL

LOW-level input voltage

VDD =2.7 V

[1] --

0.4

VDD =5.5 V

[1] --

0.5

VIH

HIGH-level input voltage

VDD =2.7 V

[1] 1.2

VDD =5.5 V

[1] 2.0

ILI

input leakage current

pin at VDD or VSS

−1-

μA

VOL

LOW-level output voltage

IOL =30 mA; VDD = 2.7 V

260

450

IOL =30 mA; VDD = 5.5 V

140

275

Open-drain output ports (P0 to P7)

IO(sink)

output sink current

LOW-level; port enabled

VOL

LOW-level output voltage

IOL = 65 mA

440

725

IOL =100 μA-

RESET

VIH

HIGH-level input voltage

VDD = 2.7 V

2.0

VDD = 5.5 V

4.8

VIL

LOW-level input voltage

VDD = 2.7 V

650

VDD = 5.5 V

900

Vhys

hysteresis voltage

VDD = 2.7 V

100

VDD = 5.5 V

200

ILI

input leakage current

pin at VDD or VSS

−1-

μA

tw(rst)L

LOW-level reset time

VI <VIL

[2] -25

trst

reset time

RESET pin; from VI > VIH

250

500

tPOR

power-on reset pulse time

RESET pin; from VI > VIH

250

500

Address pins (A0, A1, A2)

VIH

HIGH-level input voltage

VDD = 2.7 V

1.7

VDD = 5.5 V

3.5

VIL

LOW-level input voltage

VDD = 2.7 V

0.7

VDD = 5.5 V

1.5

ILI

input leakage current

pin at VDD or VSS

−1-

μA

Timing characteristics

fall time of both SDA and

SCL signals

RPU = 200 Ω; measured from

70 % VDD to 30 % VDD

-16

tv(Q)

data output valid time

[3] -

500

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