PCF8523 datasheet(45/66 Pages) NXP

45 / 66 page

PCF8523

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 30 March 2011

45 of 66

NXP Semiconductors

PCF8523

Real-Time Clock (RTC) and calendar

8.11.5 I2C-bus protocol

One I2C-bus slave address (1101000) is reserved for the PCF8523. The entire I2C-bus

slave address byte is shown in Table 44.

After a start condition, a valid hardware address has to be sent to a PCF8523 device.

The R/W bit defines the direction of the following single or multiple byte data transfer. For

the format and the timing of the START condition (S), the STOP condition (P) and the

acknowledge bit (A) refer to the I2C-bus characteristics. In the write mode, a data transfer

is terminated by sending either a STOP condition or the START condition of the next data

transfer.

Table 44.

I2C slave address byte

Slave address

Bit

MSB

LSB

0R/W

Fig 31. Bus protocol for write mode

013aaa338

slave address

00h to 13h

0 to n

data bytes

write bit

START/

STOP

acknowledge

from PCF8523

acknowledge

from PCF8523

acknowledge

from PCF8523

P/S

Fig 32. Bus protocol for read mode

013aaa339

slave address

0 to n data bytes

DATA BYTE

LAST DATA BYTE

read bit

acknowledge

from PCF8523

acknowledge

from master

no acknowledge

slave address

00h to 13h

set register

address

read register

data

write bit

STOP

acknowledge

from PCF8523

acknowledge

from PCF8523

PCF8523 Datasheet(PDF) 45 Page - NXP Semiconductors

PCF8523 Datasheet(HTML) 45 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66

Datasheet Download

Link URL