PCF85162 datasheet(35/46 Pages) NXP

35 / 46 page

PCF85162

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Product data sheet

Rev. 3 — 16 June 2011

35 of 46

NXP Semiconductors

PCF85162

Universal LCD driver for low multiplex rates

The SYNC line is provided to maintain the correct synchronization between all cascaded

PCF85162. Synchronization is guaranteed after a power-on reset. The only time that

SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in

adverse electrical environments or by defining a multiplex drive mode when PCF85162

with different SA0 levels are cascaded).

SYNC is organized as an input/output pin. The output selection is realized as an

open-drain driver with an internal pull-up resistor. A PCF85162 asserts the SYNC line at

the onset of its last active backplane signal and monitors the SYNC line at all other times.

If synchronization in the cascade is lost, it is restored by the first PCF85162 to assert

SYNC. The timing relationship between the backplane waveforms and the SYNC signal

for the various drive modes of the PCF85162 are shown in Figure 25.

The contact resistance between the SYNC on each cascaded device must be controlled.

If the resistance is too high, the device is not able to synchronize properly; this is

particularly applicable to chip-on-glass applications. The maximum SYNC contact

resistance allowed for the number of devices in cascade is given in Table 21.

(1) Is master (OSC connected to VSS).

(2) Is slave (OSC connected to VDD).

Fig 24. Cascaded PCF85162 configuration

HOST

MICRO-

PROCESSOR/

MICRO-

CONTROLLER

SDA

SCL

CLK

OSC

SYNC

32 segment drives

4 backplanes

32 segment drives

LCD PANEL

(up to 2048

elements)

PCF85162

SA0

VDD

VLCD

LCD

013aaa067

SDA

SCL

SYNC

CLK

OSC

BP0 to BP3

(open-circuit)

SA0 VSS

VSS

VDD

VLCD

PCF85162

BP0 to BP3

2CB

≤

(2)

(1)

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