Philips Semiconductors

Product data

PCA9556

2002 Mar 28

8

1

1

A2

A1 A0

0

0

1

1

A2

A1

A0

0

0

S0

A

A

A

COMMAND BYTE

acknowledge

from slave

R/W

acknowledge

from slave

A

P

NA

acknowledge

from slave

acknowledge

from master

S

DATA

DATA

R/W

first byte

at this moment master-transmitter

becomes master-receiver and

slave-receiver becomes

slave-transmitter

last byte

su01052

no acknowledge

from master

1

slave address

data from register

data from register

slave address

Figure 9. READ from register via Read byte protocol

00

1

1

A2

A1

A0

READ FROM

PORT

DATA INTO

PORT

SDA

S1

A

A

DATA 1

DATA 4

slave address

data from port

data from port

start condition

R/W

acknowledge

from slave

acknowledge

from master

stop

condition

DATA 4

DATA 2

P

DATA 3

SW00799

no acknowledge

from master

NA

NOTES:

1. This figure assumes the command byte has previously been programmed with 00h.

2. Transfer of data can be stopped at any moment by a stop condition. When this occurs, data present at the last acknowledge phase is valid

(output mode). Input data is lost.

Figure 10. READ input port register via Receive byte protocol