PCF8576_01 datasheet(15/44 Pages) PHILIPS

15 / 44 page

2001 Oct 02

Philips Semiconductors

Product speciﬁcation

Universal LCD driver for low multiplex rates

PCF8576

6.9

Segment outputs

The LCD drive section includes 40 segment outputs

pins S0 to S39 which should be connected directly to the

LCD. The segment output signals are generated in

accordance with the multiplexed backplane signals and

with data resident in the display latch. When less than

40 segment outputs are required the unused segment

outputs should be left open-circuit.

6.10

Backplane outputs

The LCD drive section includes four backplane outputs

BP0 to BP3 which should be connected directly to the

LCD. The backplane output signals are generated in

accordance with the selected LCD drive mode. If less than

four backplane outputs are required the unused outputs

can be left open-circuit. In the 1 : 3 multiplex drive mode

BP3 carries the same signal as BP1, therefore these two

adjacent outputs can be connected together to give

enhanced drive capabilities. In the 1 : 2 multiplex drive

mode BP0 and BP2, BP1 and BP3 respectively carry the

same signals and may also be paired to increase the drive

capabilities. In the static drive mode the same signal is

carried by all four backplane outputs and they can be

connected in parallel for very high drive requirements.

6.11

Display RAM

The display RAM is a static 40

× 4-bit RAM which stores

LCD data. A logic 1 in the RAM bit-map indicates the on

state of the corresponding LCD segment; similarly, a

logic 0 indicates the off state. There is a one-to-one

correspondence between the RAM addresses and the

segment outputs, and between the individual bits of a RAM

word and the backplane outputs. The first RAM column

corresponds to the 40 segments operated with respect to

backplane BP0 (see Fig.10). In multiplexed LCD

applications the segment data of the second, third and

fourth column of the display RAM are time-multiplexed

with BP1, BP2 and BP3 respectively.

When display data is transmitted to the PCF8576 the

display bytes received are stored in the display RAM in

accordance with the selected LCD drive mode. To

illustrate the filling order, an example of a 7-segment

numeric display showing all drive modes is given in Fig.11;

the RAM filling organization depicted applies equally to

other LCD types.

With reference to Fig.11, in the static drive mode the eight

transmitted data bits are placed in bit 0 of eight successive

display RAM addresses. In the 1 : 2 multiplex drive mode

the eight transmitted data bits are placed in bits 0 and 1 of

four successive display RAM addresses. In the 1 : 3

multiplex drive mode these bits are placed in

bits 0, 1 and 2 of three successive addresses, with bit 2 of

the third address left unchanged. This last bit may, if

necessary, be controlled by an additional transfer to this

address but care should be taken to avoid overriding

adjacent data because full bytes are always transmitted. In

the 1 : 4 multiplex drive mode the eight transmitted data

bits are placed in bits 0, 1, 2 and 3 of two successive

display RAM addresses.

Fig.10 Display RAM bit-map showing direct relationship between display RAM addresses and segment outputs,

and between bits in a RAM word and backplane outputs.

1234

display RAM addresses (rows) / segment outputs (S)

display RAM bits

(columns) /

backplane outputs

(BP)

MBE525

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