MSP430F2002IPWR datasheet(34/91 Pages) TI

34 / 91 page

MSP430F20x3

MSP430F20x2

MSP430F20x1

SLAS491G

– AUGUST 2005 – REVISED APRIL 2011

www.ti.com

Crystal Oscillator, XT1, Low-Frequency Mode

(1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

LFXT1 oscillator crystal

fLFXT1,LF

XTS = 0, LFXT1Sx = 0 or 1

1.8 V to 3.6 V

32768

frequency, LF mode 0, 1

LFXT1 oscillator logic level

fLFXT1,LF,logic

square wave input frequency, XTS = 0, LFXT1Sx = 3

1.8 V to 3.6 V

10000

32768

50000

LF mode

XTS = 0, LFXT1Sx = 0,

500

fLFXT1,LF = 32768 Hz, CL,eff = 6 pF

Oscillation allowance for

OALF

Ω

LF crystals

XTS = 0, LFXT1Sx = 0,

200

fLFXT1,LF = 32768 Hz, CL,eff = 12 pF

XTS = 0, XCAPx = 0

XTS = 0, XCAPx = 1

5.5

Integrated effective load

CL,eff

capacitance, LF mode(2)

XTS = 0, XCAPx = 2

8.5

XTS = 0, XCAPx = 3

XTS = 0, Measured at P1.0/ACLK,

Duty cycle, LF mode

2.2 V/3 V

fLFXT1,LF = 32768 Hz

Oscillator fault frequency,

fFault,LF

XTS = 0, LFXT1Sx = 3(4)

2.2 V/3 V

10000

LF mode(3)

(1)

To improve EMI on the XT1 oscillator, the following guidelines should be observed.

(a) Keep the trace between the device and the crystal as short as possible.

(b) Design a good ground plane around the oscillator pins.

(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.

(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.

(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.

(g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This

signal is no longer required for the serial programming adapter.

(2)

Includes parasitic bond and package capacitance (approximately 2 pF per pin).

Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a

correct setup, the effective load capacitance should always match the specification of the used crystal.

(3)

Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.

Frequencies in between might set the flag.

(4)

Measured with logic-level input frequency but also applies to operation with crystals.

Internal Very-Low-Power Low-Frequency Oscillator (VLO)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

VCC

MIN

TYP

MAX

UNIT

-40

°C to 85°C

fVLO

VLO frequency

2.2 V/3 V

kHz

105

°C

I: -40

°C to 85°C

dfVLO/dT

VLO frequency temperature drift(1)

2.2 V/3 V

0.5

°C

T: -40

°C to 105°C

dfVLO/dVCC

VLO frequency supply voltage drift(2)

°C

1.8 V to 3.6 V

%/V

(1)

Calculated using the box method:

I: (MAX(-40 to 85

°C) - MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C - (-40°C))

T: (MAX(-40 to 105

°C) - MIN(-40 to 105°C)) / MIN(-40 to 105°C) / (105°C - (-40°C))

(2)

Calculated using the box method: (MAX(1.8 to 3.6 V) - MIN(1.8 to 3.6 V)) / MIN(1.8 to 3.6 V) / (3.6 V - 1.8 V)

Timer_A

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

Internal: SMCLK, ACLK

2.2 V

fTA

Timer_A clock frequency

External: TACLK, INCLK

MHz

3 V

Duty cycle = 50%

± 10%

tTA,cap

Timer_A capture timing

TA0, TA1

2.2 V/3 V

MSP430F2002IPWR Datasheet(PDF) 34 Page - Texas Instruments

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