MSP430F2002IPWR datasheet(10/91 Pages) TI

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MSP430F20x3

MSP430F20x2

MSP430F20x1

SLAS491G

– AUGUST 2005 – REVISED APRIL 2011

www.ti.com

Table 4. Terminal Functions, MSP430F20x3

TERMINAL

NO.

DESCRIPTION

NAME

I/O

PW, N

RSA

General-purpose digital I/O pin

Timer_A, clock signal TACLK input

P1.0/TACLK/ACLK/A0+

I/O

ACLK signal output

SD16_A positive analog input A0

General-purpose digital I/O pin

Timer_A, capture: CCI0A input, compare: Out0 output

P1.1/TA0/A0-/A4+

I/O

SD16_A negative analog input A0

SD16_A positive analog input A4

General-purpose digital I/O pin

Timer_A, capture: CCI1A input, compare: Out1 output

P1.2/TA1/A1+/A4-

I/O

SD16_A positive analog input A1

SD16_A negative analog input A4

General-purpose digital I/O pin

Input for an external reference voltage/internal reference voltage output (can be

P1.3/VREF/A1-

I/O

used as mid-voltage)

SD16_A negative analog input A1

General-purpose digital I/O pin

SMCLK signal output

P1.4/SMCLK/A2+/TCK

I/O

SD16_A positive analog input A2

JTAG test clock, input terminal for device programming and test

General-purpose digital I/O pin

Timer_A, compare: Out0 output

P1.5/TA0/A2-/SCLK/TMS

I/O

SD16_A negative analog input A2

USI: external clock input in SPI or I2C mode; clock output in SPI mode

JTAG test mode select, input terminal for device programming and test

General-purpose digital I/O pin

Timer_A, capture: CCI1B input, compare: Out1 output

P1.6/TA1/A3+/SDO/SCL/

I/O

SD16_A positive analog input A3

TDI/TCLK

USI: Data output in SPI mode; I2C clock in I2C mode

JTAG test data input or test clock input during programming and test

General-purpose digital I/O pin

P1.7/A3-/SDI/SDA/

SD16_A negative analog input A3

I/O

TDO/TDI(1)

USI: Data input in SPI mode; I2C data in I2C mode

JTAG test data output terminal or test data input during programming and test

Input terminal of crystal oscillator

XIN/P2.6/TA1

I/O

General-purpose digital I/O pin

Timer_A, compare: Out1 output

Output terminal of crystal oscillator

XOUT/P2.7

I/O

General-purpose digital I/O pin(2)

Reset or nonmaskable interrupt input

RST/NMI/SBWTDIO

Spy-Bi-Wire test data input/output during programming and test

Selects test mode for JTAG pins on Port 1. The device protection fuse is

TEST/SBWTCK

connected to TEST.

Spy-Bi-Wire test clock input during programming and test

VCC

Supply voltage

VSS

Ground reference

DVCC

Digital supply voltage

AVCC

Analog supply voltage

DVSS

Digital ground reference

AVSS

Analog ground reference

QFN Pad

Pad

QFN package pad. Connection to VSS is recommended.

(1)

TDO or TDI is selected via JTAG instruction.

(2)

If XOUT/P2.7 is used as an input, excess current flows until P2SEL.7 is cleared. This is due to the oscillator output driver connection to

this pad after reset.

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