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MSP430F1132IPW Datasheet(PDF) 19 Page - Texas Instruments

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Part # MSP430F1132IPW
Description  MIXED SIGNAL MICROCONTROLLER
PDF  52 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

MSP430F1132IPW Datasheet(HTML) 19 Page - Texas Instruments

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MSP430x11x2, MSP430x12x2
MIXED SIGNAL MICROCONTROLLER
SLAS361D − JANUARY 2002 − REVISED AUGUST 2004
19
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
outputs Port 1 to Port 3; P1.0 to P1.7, P2.0 to P2.5, P3.0 to P3.7
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I(OHmax) = −1.5 mA
See Note 1
VCC−0.25
VCC
I(OHmax) = −6 mA
VCC = 2.2 V
See Note 2
VCC−0.6
VCC
VOH
High-level output voltage
I(OHmax) = −1.5 mA
See Note 1
VCC−0.25
VCC
V
I(OHmax) = −6 mA
VCC = 3 V
See Note 2
VCC−0.6
VCC
I(OLmax) = 1.5 mA
See Note 1
VSS
VSS+0.25
I(OLmax) = 6 mA
VCC = 2.2 V
See Note 2
VSS
VSS+0.6
VOL
Low-level output voltage
I(OLmax) = 1.5 mA
See Note 1
VSS
VSS+0.25
V
I(OLmax) = 6 mA
VCC = 3 V
See Note 2
VSS
VSS+0.6
NOTES:
1. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±12 mA to hold the maximum voltage
drop specified.
2. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±48 mA to hold the maximum voltage
drop specified.
outputs P1.x, P2.x, P3.x, TAx
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
f(P20)
P2.0/ACLK, CL = 20 pF
2.2 V/3 V
fSystem
f(TAx)
Output frequency
TA0, TA1, TA2, CL = 20 pF,
Internal clock source, SMCLK signal applied (see Note 1)
2.2 V/3 V
dc
fSystem
MHz
fSMCLK = fLFXT1 = fXT1
40%
60%
fSMCLK = fLFXT1 = fLF
35%
65%
P1.4/SMCLK,
CL = 20 pF
fSMCLK = fLFXT1/n
2.2 V/3 V
50%−
15 ns
50%
50%+
15 ns
t(Xdc)
Duty cycle of O/P
frequency
fSMCLK = fDCOCLK
2.2 V/3 V
50%−
15 ns
50%
50%+
15 ns
frequency
fP20 = fLFXT1 = fXT1
40%
60%
P2.0/ACLK,
fP20 = fLFXT1 = fLF
2.2 V/3 V
30%
70%
CL = 20 pF
fP20 = fLFXT1/n
50%
t(TAdc)
TA0, TA1, TA2,
CL = 20 pF, Duty cycle = 50%
2.2 V/3 V
0
±50
ns
NOTES:
1. The limits of the system clock MCLK has to be met. MCLK and SMCLK can have different frequencies.



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