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TMS320F2812 Datasheet(PDF) 103 Page - Texas Instruments

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Part # TMS320F2812
Description  Digital Signal Processors
PDF  170 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320F2812 Datasheet(HTML) 103 Page - Texas Instruments

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XCLKOUT
(A)(B)
XCLKIN
(A)
C10
C3
C4
C9
C5
C8
C1
C6
TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
www.ti.com
SPRS174S – APRIL 2001 – REVISED MARCH 2011
6.14.2 Output Clock Characteristics
Table 6-10. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)(1)(2)
NO.
PARAMETER
MIN
TYP
MAX
UNIT
C1
tc(XCO)
Cycle time, XCLKOUT
6.67(3)
ns
C3
tf(XCO)
Fall time, XCLKOUT
2
ns
C4
tr(XCO)
Rise time, XCLKOUT
2
ns
C5
tw(XCOL)
Pulse duration, XCLKOUT low
H – 2
H + 2
ns
C6
tw(XCOH)
Pulse duration, XCLKOUT high
H – 2
H + 2
ns
C7
tp
PLL lock time(4)
131072tc(CI)
ns
(1)
A load of 40 pF is assumed for these parameters.
(2)
H = 0.5tc(XCO)
(3)
The PLL must be used for maximum frequency operation.
(4)
This parameter has changed from 4096 XCLKIN cycles in the earlier revisions of the silicon.
A.
The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown in
Figure 6-10 is intended to illustrate the timing parameters only and may differ based on configuration.
B.
XCLKOUT configured to reflect SYSCLKOUT.
Figure 6-10. Clock Timing
6.15 Reset Timing
Table 6-11. Reset (XRS) Timing Requirements(1)
MIN
NOM
MAX
UNIT
tw(RSL1)
Pulse duration, stable XCLKIN to XRS high
8tc(CI)
cycles
tw(RSL2)
Pulse duration, XRS low
Warm reset
8tc(CI)
cycles
Pulse duration, reset pulse generated by
tw(WDRS)
512tc(CI)
cycles
watchdog
Delay time, address/data valid after XRS
td(EX)
32tc(CI)
cycles
high
tOSCST
(2)
Oscillator start-up time
1
10
ms
tsu(XPLLDIS)
Setup time for XPLLDIS pin
16tc(CI)
cycles
th(XPLLDIS)
Hold time for XPLLDIS pin
16tc(CI)
cycles
th(XMP/MC)
Hold time for XMP/MC pin
16tc(CI)
cycles
th(boot-mode)
Hold time for boot-mode pins
2520tc(CI)
(3)
cycles
(1)
If external oscillator/clock source are used, reset time has to be low at least for 1 ms after VDD reaches 1.5 V.
(2)
Dependent on crystal/resonator and board design.
(3)
The boot ROM reads the password locations. Therefore, this timing requirement includes the wakeup time for flash. See the
TMS320x281x DSP Boot ROM Reference Guide (literature number SPRU095) and the TMS320x281x DSP System Control and
Interrupts Reference Guide (literature number SPRU078) for further information.
Copyright © 2001–2011, Texas Instruments Incorporated
Electrical Specifications
103
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Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812



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