TMS320LC2401AVFS datasheet(27/88 Pages) TI

27 / 88 page

TMS320LF2401A, TMS320LC2401A

DSP CONTROLLERS

SPRS161K − MARCH 2001 − REVISED JULY 2007

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

functional block diagram of the 2401A DSP CPU

Data Bus

OSCALE (0−7)

ACCL(16)

ACCH(16)

CALU(32)

MUX

ISCALE (0−16)

MUX

PREG(32)

Multiplier

TREG0(16)

MUX

B1 (256

× 16)

B2 (32

× 16)

DARAM

B0 (256

× 16)

DARAM

LSB

from

MUX

DP(9)

MUX

ARAU(16)

ARB(3)

ARP(3)

Program Bus

AR7(16)

AR6(16)

AR5(16)

AR3(16)

AR2(16)

AR1(16)

AR0(16)

Stack 8

× 16

MUX

XTAL2

CLKOUT

XTAL1

AR4(16)

Data/Prog

PSCALE (−6, 0, 1, 4)

Data

FLASH EEPROM

MUX

NPAR

PAR

MSTACK

Program Control

(PCTRL)

Memory Map

IMR (16)

IFR (16)

GREG (16)

XINT[1−2]

NOTES: A. See Table 4 for symbol descriptions.

B. For clarity, the data and program buses are shown as single buses although they include address and data bits.

C. Refer to the TMS320F/C24x DSP Controllers Reference Guide: CPU and Instruction Set (literature number SPRU160) for CPU

instruction set information.

TMS320LC2401AVFS Datasheet(PDF) 27 Page - Texas Instruments

TMS320LC2401AVFS Datasheet(HTML) 27 Page - Texas Instruments

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