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TMS320F28035RSHT Datasheet(PDF) 93 Page - Texas Instruments |
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TMS320F28035RSHT Datasheet(HTML) 93 Page - Texas Instruments |
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93 / 157 page  GPxDAT (read) Input Qualification GPxMUX1/2 HighImpedance OutputControl GPIOxpin XRS 0=Input,1=Output LowP ower ModesBlock GPxDIR(latch) Peripheral2Input Peripheral3Input Peripheral1Output Peripheral2Output Peripheral3Output Peripheral1OutputEnable Peripheral2OutputEnable Peripheral3OutputEnable 00 01 10 11 00 01 10 11 00 01 10 11 GPxCTRL Peripheral1Input N/C GPxPUD LPMCR0 Internal Pullup GPIOLMPSEL GPxQSEL1/2 GPxSET GPxDAT (latch) GPxCLEAR GPxTOGGLE =DefaultatReset PIE ExternalInterrupt MUX Asynchronous path Asynchronouspath GPIOXINT1SEL GPIOXINT2SEL GPIOXINT3SEL TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com SPRS584E – APRIL 2009 – REVISED MARCH 2011 A. x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR register depending on the particular GPIO pin selected. B. GPxDAT latch/read are accessed at the same memory location. C. This is a generic GPIO MUX block diagram. Not all options may be applicable for all GPIO pins. See the TMS320x2803x Piccolo System Control and Interrupts Reference Guide (literature number SPRUGL8) for pin-specific variations. Figure 4-17. GPIO Multiplexing Copyright © 2009–2011, Texas Instruments Incorporated Peripherals 93 Submit Documentation Feedback focus.ti.com: TMS320F28030 TMS320F28031 TMS320F28032 TMS320F28033 TMS320F28034 TMS320F28035 |
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