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TMS320F28035RSHT Datasheet(PDF) 13 Page - Texas Instruments |
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TMS320F28035RSHT Datasheet(HTML) 13 Page - Texas Instruments |
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13 / 157 page  TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com SPRS584E – APRIL 2009 – REVISED MARCH 2011 Table 2-2. Terminal Functions(1) (continued) TERMINAL I/O/Z DESCRIPTION PN PAG RSH NAME PIN # PIN # PIN # ADCINA1 17 14 12 I ADC Group A, Channel 1 input ADC Group A, Channel 0 input. NOTE: VREFHI and ADCINA0 share the same pin on the 64-pin PAG device and ADCINA0 18 15 13 I their use is mutually exclusive to one another. NOTE: VREFHI and ADCINA0 share the same pin on the 56-pin RSH device and their use is mutually exclusive to one another. ADC External Reference – only used when in ADC external reference mode. See Section 4.2.1, ADC. NOTE: VREFHI and ADCINA0 share the same pin on the 64-pin PAG device and VREFHI 19 15 13 I their use is mutually exclusive to one another. NOTE: VREFHI and ADCINA0 share the same pin on the 56-pin RSH device and their use is mutually exclusive to one another. ADCINB7 30 24 21 I ADC Group B, Channel 7 input ADCINB6 29 23 20 I ADC Group B, Channel 6 input COMP3B I Comparator Input 3B AIO14 I/O Digital AIO 14 ADCINB5 28 – – I ADC Group B, Channel 5 input ADCINB4 27 22 19 I ADC Group B, Channel 4 input COMP2B I Comparator Input 2B AIO12 I/O Digital AIO12 ADCINB3 26 21 18 I ADC Group B, Channel 3 input ADCINB2 25 20 17 I ADC Group B, Channel 2 input COMP1B I Comparator Input 1B AIO10 I/O Digital AIO 10 ADCINB1 24 19 16 I ADC Group B, Channel 1 input ADCINB0 23 18 – I ADC Group B, Channel 0 input NOTE: VREFLO is always connected to VSSA on the 64-pin PAG device and on the VREFLO 22 17 15 I 56-pin RSH device. CPU AND I/O POWER VDDA 20 16 14 Analog Power Pin. Tie with a 2.2- μF capacitor (typical) close to the pin. Analog Ground Pin. VSSA 21 17 15 NOTE: VREFLO is always connected to VSSA on the 64-pin PAG device and on the 56-pin RSH device. VDD 7 5 3 CPU and Logic Digital Power Pins – no supply source needed when using internal VREG. Tie with 1.2 µF (minimum) ceramic capacitor (10% tolerance) to VDD 54 43 38 ground when using internal VREG. Higher value capacitors may be used, but VDD 72 59 52 could impact supply-rail ramp-up time. VDDIO 36 29 26 Digital I/O and Flash Power Pin – Single Supply source when VREG is enabled VDDIO 70 57 50 VSS 8 6 4 VSS 35 28 25 Digital Ground Pins VSS 53 42 37 VSS 71 58 51 Copyright © 2009–2011, Texas Instruments Incorporated Introduction 13 Submit Documentation Feedback focus.ti.com: TMS320F28030 TMS320F28031 TMS320F28032 TMS320F28033 TMS320F28034 TMS320F28035 |
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