SC1405

HIGH SPEED SYNCHRONOUS POWER

MOSFET SMART DRIVER

© 2000 SEMTECH CORP.

652 MITCHELL ROAD NEWBURY PARK CA 91320

August 31, 2000

5

PIN CONFIGURATION

NOTE:

(1) All logic level inputs and outputs are open collector TTL compatible.

PIN DESCRIPTION

Pin #

Pin Name

Pin Function

1

OVP_S

Overvoltage protection sense. External scaling resistors required to set

protection threshold.

2

EN

When high, this pin enables the internal circuitry of the device. When

low, TG, BG and PRDY are forced low and the supply current (5V) is

less than 10µA.

3

GND

Logic GND.

4

CO

TTL-level input signal to the MOSFET drivers.

5

S_MOD

When low, this signal forces BG to be low. When high, BG is not a

function of this signal.

6

DELAY_C

Sets the additional propagation delay for BG going low to TG going high.

Total propagation delay= 20ns + 1ns/pF.

7

PRDY

This pin indicates the status of 5V. When 5V is less than 4.4V(typ) this

output is driven low. When 5V is greater than or equals to 4.4V(typ) this

output is driven to 5V level. This output has a 10mA drive capability and

10µA sink capability.

8V

CC

+5V supply. A .22-1µF ceramic capacitor should be connected from 5V

to PGND very close to this pin.

9

BG

Output drive for the synchronous MOSFET.

10

PGND

Power ground. Connect to the synchronous FET power ground.

11

DSPS_DR

Dynamic Set Point Switch Drive. TTL level output signal. When S_MOD

is high, this pin follows the BG driver pin voltage.

12

DRN

This pin connects to the junction of the switching and synchronous

MOSFET’s. This pin can be subjected to a -2V minimum relative to

PGND without affecting operation.

13

TG

Output gate drive for the switching (high-side) MOSFET.

14

BST

Bootstrap pin. A capacitor is connected between BST and DRN pins to

develop the floating bootstrap voltage for the high-side MOSFET. The

capacitor value is typically between 0.1µF and 1µF (ceramic).