TMS570LS3137 datasheet(109/159 Pages) TI

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r(ETM)

h(ETM)

l(ETM)

f(ETM)

cyc(ETM)

TMS570LS3137

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SPNS162.

– SEPTEMBER 2011

4.21.7 Embedded Trace Macrocell (ETM-R4)

The device contains a ETM-R4 module with a 32-bit internal data port. The ETM-R4 module is connected

to a TPIU with a 32-bit data bus; the TPIU provides a 35-bit (32-bit data, 3-bit control) external interface

for trace. The ETM-R4 is CoreSight compliant and follows the ETM v3 specification; for more details see

ARM CoreSight ETM-R4 TRM specification.

4.21.7.1 ETM TRACECLKIN Selection

The ETM clock source can be selected as either VCLK or the external ETMTRACECLKIN pin. The

selection is done by the EXTCTRLOUT[1:0] control bits of the TPIU; the default is '00'. The address of this

Before you begin accessing TPIU registers, TPIU should be unlocked via coresight key and 1 or 2 should

be written to this register.

Table 4-40. TPIU / TRACECLKIN Selection

EXTCTRLOUT[1:0]

TPIU/TRACECLKIN

tied-zero

VCLK

ETMTRACECLKIN

tied-zero

4.21.7.2 Timing Specifications

Figure 4-22. ETMTRACECLKOUT Timing

Table 4-41. ETMTRACECLK Timing

Parameter

MIN

Description

tcyc(ETM)

t(HCLK) * 4

Clock period

tl(ETM)

20ns

Low pulse width

th(ETM)

20ns

High pulse width

tr(ETM)

3ns

Clock and data rise time

tf(ETM)

3ns

Clock and data fall time

System Information and Electrical Specifications

109

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