FM25640C datasheet(8/13 Pages) RAMTRON

8 / 13 page

FM25640C - 64Kb 5V SPI F-RAM

Rev. 1.1

June 2011

8 of 13

op-code

MSB

13-bit Address

12 11 10

LSB MSB

LSB

SCK

Data

Figure 9. Memory Write

op-code

MSB

13-bit Address

12 11 10

LSB MSB

LSB

SCK

Data

Figure 10. Memory Read

Endurance

Internally, a F-RAM operates with a read and restore

mechanism. Therefore, endurance cycles are applied

for each access: read or write. The

F-RAM

architecture is based on an array of rows and

columns. Each access causes a cycle for an entire

row. In the FM25640C, a row is 64 bits wide. Every

8-byte boundary marks the beginning of a new row.

Endurance can be optimized by ensuring frequently

accessed

data

located

different

rows.

Regardless, F-RAM read and write endurance is

effectively unlimited at the 20MHz clock speed.

Even at 2000 accesses per second to the same row, 15

years time will elapse before 10

12 endurance cycles

occur.

FM25640C Datasheet(PDF) 8 Page - Ramtron International Corporation

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