AN601 datasheet(3/8 Pages) VISHAY

3 / 8 page

AN601

Vishay Siliconix

Document Number: 70572

15-Feb-94

www.vishay.com

S FaxBack 408-970-5600

DRAIN

GATE

SOURCE

DRAIN

GATE

SOURCE

Pp+

epi n–

SUBSTRATE n+

FIGURE 3. Equivalent Circuit and Cross Section

Examination of Figure 3 suggests that the current necessary

to trigger this series of events might be closely approximated

if both the VBE of the parasitic npn bipolar transistor and Rp

were known.[7] Test patterns available on the semiconductor

wafer during manufacture make it possible to examine such

parameters

the

parasitic

npn

bipolar

transistor.

Measurement results of VBE, beta, and Rp+ from the test

pattern are shown in Figure

4. Because of the deep p+

diffusion that forms the Zener structure, the region beneath the

n+ diffusion — where Rp is critical—resembles a graded

junction. This—in concert with the dramatic temperature rise

that together reduces VBE, raises Rp, and increases

beta—com- complicates any effort to calculate the critical

avalanche current required to excite the parasitic bipolar

transistor. Blackburn[8] derived a worst-case calculation;

however, the actual performance is substantially better than

predicted due to second-order effects.

Today’s MOSPOWER devices can safely withstand over two

times the 25

_C rated current even at junction temperatures

approaching 150

_C. The “active” form of failure is no longer the

prevalent mode under normal operating conditions. The

limiting mechanism is now usually a thermal failure caused by

the large temperature increase during avalanche.

The Thermal Effect — The “Passive” Mode. During UIS, as the

MOSFET is subjected to increasing energy, the internal chip

temperature rises dramatically (equation 4) and is thought to

generate a mesoplasma. Such mesoplasmas (regenerative

heating) lead to the irreversible damage generally associated

with thermal runaway.[1] * The swiftness of this temperature

rise, see equation (3), tends to make heat sinks irrelevant for

UIS testing.

100

150

200

250

0.6

0.5

0.4

0.3

0.2

0.1

900

800

700

300

600

500

400

120

100

BETA

VBE

W/V

Temperature (

_C)

(BETA)

(VBE)

(

W/V)

FIGURE 4. Parasitic Bipolar Transistor Characteristics

During this avalanche period, as defined by equation (3),

energy is dissipated in the device equation (2), resulting in a

dramatic increase in chip temperature. Blackburn[8] derived

the following one-dimensional thermal model to calculate the

maximum temperature rise,

DTM.

*The increasing temperature during mesoplasma formation results in a decreasing thermal conductivity of silicon (see Figure 5a) which, in turn,

results in a further increase in the localized temperature. Thermal runaway is thus encouraged.

AN601 Datasheet(PDF) 3 Page - Vishay Siliconix

AN601 Datasheet(HTML) 3 Page - Vishay Siliconix

Html Pages

1 2 3 4 5 6 7 8

Datasheet Download

Link URL