AN601

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Document Number: 70572

15-Feb-94

where

(4)

maximum instantaneous

temperature rise (

_C)

and

DT

2

3

K

+

2

A (r

pkc)

+ 2

R

pC

A

=

the active chip area (where heat originates)

r

=

the density of silicon

k

=

the thermal conductivity (very temperature

dependent (see Figure 5a)

c

=

the specific heat of silicon (also

temperature dependent (see Figure 1b)

R

=

effective thermal resistance of chip (

_C/W)

C

=

effective thermal capacitance of chip (J/

_C)

Equation (4) can be further manipulated to relate the

temperature rise,

(5)

DT

2

3

L

l

o

V

(BR)eff

assume it is a constant. Therefore,

(6)

(7)

DT

L

l

o

or

DT

3 2

o

L

1400

0

200

400

600

800

1000

1200

1000

800

0

600

400

200

Temperature (K)

1.4

–40

40

120

200

280

360

1.2

1.0

0.8

0

0.6

0.4

0.2

Temperature (

_C)

Figure 5a.

Conductivity of Silicon vs. Temperature

([Physics Review, Vol. 130 (6/’63)] (

W/cm_)

Figure 1b.

Specific Heat of Silicon vs. Temperature

(

W sec/gm_)

If we assume L is constant, equation (7) is further reduced to

(8)

DT

3 2

o

which further identifies that

(9)

DT

3 4

If the parasitic bipolar transistor is

not excited, equation (9)

relates the peak temperature rise to the avalanche energy

dissipation. This temperature rise then becomes the cause of

the other failure mode referred to as “passive.”