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HT48R063B Datasheet(PDF) 14 Page - Holtek Semiconductor Inc |
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HT48R063B Datasheet(HTML) 14 Page - Holtek Semiconductor Inc |
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14 / 84 page  Symbol Parameter Test Conditions Min. Typ. Max. Unit VDD Conditions fERC System Clock (ERC) 5V Ta=25 °C, R=120kW * -2% 4 +2% MHz 5V Ta=0~70 °C, R=120kW * -5% 4 +5% MHz 5V Ta= -40°C~85°C, R=120k W * -7% 4 +7% MHz 2.2V~ 5.5V Ta= -40°C~85°C, R=120k W * -11% 4 +11% MHz fLXT System Clock (LXT) ¾¾ ¾ 32768 ¾ Hz fTIMER Timer Input Frequency (TCn) ¾ 2.2V~5.5V 0 ¾ 4000 kHz 3.0V~5.5V 0 ¾ 8000 kHz 4.5V~5.5V 0 ¾ 12000 kHz fLIRC LIRC Oscillator 3V ¾ 5 10 15 kHz 5V ¾ 6.5 13 19.5 kHz tRES External Reset Low Pulse Width ¾¾ 1 ¾¾ ms tSST System Start-up time Period ¾ For HXT/LXT ¾ 128 ¾ tSYS For ERC/IRC (By configuration option) ¾ 2 ¾ tSYS tINT Interrupt Pulse Width ¾¾ 1 ¾¾ ms tLVR Low Voltage Width to Reset ¾¾ 0.25 1 2 ms RESTD Reset Delay Time ¾¾ ¾ 100 ¾ ms Note: 1. tSYS=1/fSYS 2. *For fERC, as the resistor tolerance will influence the frequency a precision resistor is recommended. 3. To maintain the accuracy of the internal HIRC oscillator frequency, a 0.1 mF decoupling capacitor should be connected between VDD and VSS and located as close to the device as possible. Power-on Reset Characteristics Symbol Parameter Test Conditions Min. Typ. Max. Unit VDD Conditions VPOR VDD Start Voltage to Ensure Power-on Reset ¾¾¾ ¾ 100 mV RRVDD VDD raising rate to Ensure Power-on Reset ¾¾ 0.035 ¾¾ V/ms tPOR Minimum Time for VDD Stays at VPOR to Ensure Power-on Reset ¾¾ 1 ¾¾ ms HT48R063B/064B/065B/066B Rev. 1.00 14 April 7, 2011 Ta=25 °C T i m e V D D V P O R R R V D D t P O R |
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