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HT82V46 Datasheet(PDF) 5 Page - Holtek Semiconductor Inc |
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HT82V46 Datasheet(HTML) 5 Page - Holtek Semiconductor Inc |
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5 / 27 page  Rev. 1.10 5 November 24, 2011 HT82V46 Symbol Parameter Test Conditions Min. Typ. Max. Unit Programmable Gain Amplifier Resolution ― ― 9 ― bits Gain Equation ― 0.66 + PGA[8:0] * 7.34 / 511 V/V GMAX Max Gain, Each Channel ― ― 7.5 ― V/V GMIN Min Gain, Each Channel ― ― 0.65 ― V/V Channel Matching ― ― 1 5 % A/D Converter Resolution ― ― 16 ― bits Speed ― ― 45 ― MSPS Full-scale Input Range 2*(VRT - VRB) LOWREF=0 ― 2.0 ― V LOWREF=1 1.2 V Supply Currents Total Supply Current ― ― 160 ― mA Analogue Supply Current ― ― 130 ― mA Digital Supply Current ― ― 30 ― mA Power Down Mode ― ― 130 ― μA Note:1.Full-scaleinputvoltagedenotesthepeakinputsignalamplitudethatcanbegainedtomatchtheADCfull- scaleinputrange. 2.Inputsignallimitsarethelimitswithinwhichthefull-scaleinputvoltagesignalmustlie. Timing Specification AVDD=DVDD=3.3V, AVSS=DVSS=0V, TA=25°C, ADCK=45MHz unless otherwise stated. Symbol Parameter Test Conditions Min. Typ. Max. Unit Clock Parameter tADC ADCK Period ― 22 ― ― ns tADH ADCK High Period ― 10 11 ― ns tADL ADCK Low Period ― 10 11 ― ns tC1 CDS1 Pulse High ― 5 ― ― ns tC2 CDS2 Pulse High ― 5 ― ― ns tC1FC2R CDS1 Falling to CDS2 Rising ― 0 ― ― ns tADFC2R ADCK Falling to CDS2 Rising ― 4 ― ― ns tADRC2R ADCK Rising to CDS2 Rising ― 2.5 ― ― ns tADFC2F ADCK Falling to CDS2 Falling ― 4 ― ― ns tC2FADR CDS2 Falling to ADCK Rising 2 ― 1 ― ― ns tADFC1R 1st ADCK Falling after CDS2 Falling to CDS1 Rising ― 1 ― ― ns tPR3 3-channel Mode Pixel Rate ― 66 ― ― ns tPR2 2-channel Mode Pixel Rate ― 44 ― ― ns tPR1 1-channel Mode Pixel Rate ― 22 ― ― ns tOD Output Propagation Delay ― ― 8 12 ns LAT Output Latency. From 1st ADCK Rising Edge after CDS2 Falling to Data Output ― ― 7 ― ADCK periods |
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