1626

09/17/09

ICS9DS400

Four Output Differential Buffer for PCIe for Gen 2 with Spread

12

Advance Information

Pin #

Name

Control Function

Type

0

1

Default

Bit 7

PD_Mode

PD# drive mode

RW

driven

Hi-Z

0

Bit 6

STOP_Mode

SRC_Stop# drive mode

RW

driven

Hi-Z

0

Bit 5

0

Bit 4

SPREAD_AMT(1)

Spread % MSB

RW

Latch

Bit 3

SPREAD_AMT(0)

Spread % LSB

RW

1

Bit 2

SPREAD_EN

Turns on spread

RW

SS Off

SS On

Latch

Bit 1

BYPASS#

BYPASS#_SSCG

RW

fan-out

SSCG

Latch

Bit 0

Byte0 CONTROL

Selects control source of Byte 0

RW

Smbus

Input Pins

1

SMBus Table: Output Control Register

Pin #

Name

Control Function

Type

0

1

Default

Bit 7

Reserved

Reserved

RW

1

Bit 6

DIF_6

Output Enable

RW

Disable

Enable

1

Bit 5

DIF_5

Output Enable

RW

Disable

Enable

1

Bit 4

Reserved

Reserved

RW

1

Bit 3

Reserved

Reserved

RW

1

Bit 2

DIF_2

Output Enable

RW

Disable

Enable

1

Bit 1

DIF_1

Output Enable

RW

Disable

Enable

1

Bit 0

Reserved

Reserved

RW

1

NOTE: The SMBus Output Enable Bit must be '1' AND the respective OE pin must be active for the output to run!

SMBus Table: OE Pin Control Register

Pin #

Name

Control Function

Type

0

1

Default

Bit 7

Reserved

Reserved

RW

0

Bit 6

DIF_6

DIF_6 Stoppable with OE6

RW

Free-run

Stoppable

0

Bit 5

Reserved

Reserved

RW

0

Bit 4

Reserved

Reserved

RW

0

Bit 3

Reserved

Reserved

RW

0

Bit 2

Reserved

Reserved

RW

0

Bit 1

DIF_1

DIF_1 Stoppable with OE1

RW

Free-run

Stoppable

0

Bit 0

Reserved

Reserved

RW

0

SMBus Table: Reserved Register

Pin #

Name

Control Function

Type

0

1

Default

Bit 7

X

Bit 6

X

Bit 5

X

Bit 4

X

Bit 3

X

Bit 2

X

Bit 1

X

Bit 0

X

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

-

-

Reserved

6,7

-

Byte 3

-

-

-

9,10

-

Byte 2

-

-

6,7

22,23

22,23

19,20

Byte 1

-

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Byte 0

-

-

-

Reserved

1

00 = -0.125%

01 = -0.25%

10 = -0.375%

11 = -0.50%

-

28

22

-

Notes: Pins 1, 22 and 28 are latched into Byte 0 on the first power up of the device. Bits [4:1] will NOT reflect

changes in these pin states after power up, even though the pins are controlling the function of the part. Setting

Byte 0 bit 0 to 0 allows the SMBus to write Bits [4:1] and transfers control of the functions from the pins to SMBus.

Once Byte 0 bit 0 is set to 0, the pins no longer impact Byte 0, bits [4:1] or the device function.