74AUP2G08

All information provided in this document is subject to legal disclaimers.

© NXP B.V. 2011. All rights reserved.

Product data sheet

Rev. 5 — 1 December 2011

2 of 21

NXP Semiconductors

74AUP2G08

Low-power dual 2-input AND gate

3.

Ordering information

4.

Marking

[1]

The pin 1 indicator is located on the lower left corner of the device, below the marking code.

5.

Functional diagram

Table 1.

Ordering information

Type number

Package

Temperature range

Name

Description

Version

74AUP2G08DC

40 C to +125 C

VSSOP8

plastic very thin shrink small outline package; 8 leads;

body width 2.3 mm

SOT765-1

74AUP2G08GT

40 C to +125 C

XSON8

plastic extremely thin small outline package; no leads;

8 terminals; body 1

 1.95  0.5 mm

SOT833-1

74AUP2G08GF

40 C to +125 C

XSON8

extremely thin small outline package; no leads;

8 terminals; body 1.35

 1  0.5 mm

SOT1089

74AUP2G08GD

40 Cto +125 C

XSON8U

plastic extremely thin small outline package; no leads;

8 terminals; UTLP based; body 3

 2  0.5 mm

SOT996-2

74AUP2G08GM

40 C to +125 C

XQFN8U

plastic extremely thin quad flat package; no leads;

8 terminals; UTLP based; body 1.6

 1.6  0.5 mm

SOT902-1

74AUP2G08GN

40 C to +125 C

XSON8

extremely thin small outline package; no leads;

8 terminals; body 1.2

 1.0  0.35 mm

SOT1116

74AUP2G08GS

40 C to +125 C

XSON8

extremely thin small outline package; no leads;

8 terminals; body 1.35

 1.0  0.35 mm

SOT1203

Table 2.

Marking codes

Type number

Marking code[1]

74AUP2G08DC

p08

74AUP2G08GT

p08

74AUP2G08GF

pE

74AUP2G08GD

p08

74AUP2G08GM

p08

74AUP2G08GN

pE

74AUP2G08GS

pE

Fig 1.

Logic symbol

Fig 2.

IEC logic symbol

Fig 3.

Logic diagram (one gate)

001aah788

1A

1B

1Y

2A

2B

2Y

001aah789

&

&

mna221

A

B

Y