HT82A834R datasheet(13/49 Pages) HOLTEK

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HT82A834R

Rev. 1.00

August 27, 2007

WDT

² and the other set ²CLR WDT1² and ²CLR

WDT2

². Of these two types of instruction, only one type

of instruction can be active at a time depending on the

configuration option

²CLR WDT² times selection option.

If the

²CLR WDT² is selected (i.e., CLR WDT times

equal one), any execution of the

²CLR WDT² instruction

clears the WDT. In the case that

²CLR WDT1² and ²CLR

WDT2

² are chosen (i.e., CLR WDT times equal two),

these two instructions have to be executed to clear the

WDT; otherwise, the WDT may reset the chip due to a

time-out.

Power Down Operation

- HALT

The HALT mode is initialized by the

²HALT² instruction

and results in the following:

· The system oscillator will be turned off but the WDT

oscillator remains running (if the WDT oscillator is se-

lected).

· The contents of the on-chip RAM and registers remain

unchanged.

· The WDT and WDT prescaler will be cleared and re-

counted again (if the WDT clock is from the WDT os-

cillator).

· All of the I/O ports remain in their original status.

· The PDF flag is set and the TO flag is cleared.

The system can leave the HALT mode by means of an

external reset, an interrupt, an external falling edge sig-

nal on port A or a WDT overflow. An external reset

causes a device initialization and the WDT overflow per-

forms a

²warm reset². After the TO and PDF flags are

examined, the cause for chip reset can be determined.

The PDF flag is cleared by a system power-up or exe-

cuting the

²CLR WDT² instruction and is set when exe-

cuting the

²HALT² instruction. The TO flag is set if a

WDT time-out occurs, and causes a wake-up that only

resets the program counter and stack pointer; the others

remain in their original status.

The port A wake-up and interrupt methods can be con-

sidered as a continuation of normal execution. Each bit

in port A can be independently selected to wake-up the

device by configuration option. Awakening from an I/O

port stimulus, the program will resume execution of the

next instruction. If it awakens from an interrupt, two se-

quence may occur. If the related interrupt is disabled or

the interrupt is enabled but the stack is full, the program

will resume execution at the next instruction. If the inter-

rupt is enabled and the stack is not full, the regular inter-

rupt response takes place. If an interrupt request flag is

set to

²1² before entering the HALT mode, the wake-up

function of the related interrupt will be disabled. Once a

wake-up event occurs, it takes 1024 tSYS (system clock

period) to resume normal operation. In other words, a

dummy period will be inserted after a wake-up. If the

wake-up results from an interrupt acknowledge signal,

the actual interrupt subroutine execution will be delayed

by one or more cycles. If the wake-up results in the next

instruction execution, this will be executed immediately

after the dummy period is finished.

To minimize power consumption, all the I/O pins should

be carefully managed before entering the HALT status.

The ADC, DAC and PA will all be powered down when in

the HALT mode.

Reset

There are four ways in which a reset can occur:

· RES reset during normal operation

· RES reset during HALT

· WDT time-out reset during normal operation

· USB reset

The

time-out during HALT is different from other

chip reset conditions, since it can perform a

²warm re -

set

² that resets only the program counter and stack

pointer, leaving the other circuits in their original state.

Some registers remain unchanged during other reset

conditions. Most registers are reset to the

²initial condi-

tion

² when the reset conditions are met. By examining

the PDF and TO flags, the program can distinguish be-

tween different

²chip resets².

PDF

RESET Conditions

RESET reset during power-up

RESET reset during normal operation

RESET wake-up HALT

WDT time-out during normal operation

WDT wake-up HALT

Note:

²u² stands for ²unchanged²

To guarantee that the system oscillator is started and

stabilized, the SST (System Start-up Timer) provides an

extra delay of 1024 system clock pulses when the sys-

tem resets (power-up, WDT time-out or RES reset) or

the system awakes from the HALT state.

When a system reset occurs, the SST delay is added

during the reset period. Any wake-up from HALT will en-

able the SST delay.

The functional unit chip reset status are shown below.

Program Counter

000H

Interrupt

Disable

WDT

Clear. After master reset,

WDT begins counting

Timer/event Counter

Off

Input/output Ports

Input mode

Stack Pointer

Points to the top of the stack

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