HT82A834R datasheet(21/49 Pages) HOLTEK

21 / 49 page

HT82A834R

Rev. 1.00

August 27, 2007

Bit No.

Label

R/W

Power-on

Functions

ASET

R/W

This bit is used to configure the SIE to automatically change the device

address by the value stored in the AWR register. When this bit is set to

²1² by firmware, the SIE will update the device address by the value

stored in the AWR register after the PC host has successfully read the

data from the device by an IN operation. Otherwise, when this bit is

cleared to

²0², the SIE will update the device address immediately after

an address is written to the AWR register. So, in order to work properly,

the firmware has to clear this bit after a next valid SETUP token is

received.

ERR

R/W

This bit is used to indicate that some errors have occurred when the

FIFO is accessed. This bit is set by SIE and should be cleared by

firmware. This bit is used for all endpoint.

OUT

R/W

This bit is used to indicate the OUT token (except the OUT zero length

token) has been received. The firmware clears this bit after the OUT

data has been read. Also, this bit will be cleared by SIE after the next

valid SETUP token is received.

3IN

This bit is used to indicate the current USB receiving signal from PC

host is an IN token.

NAK

This bit is used to indicate the SIE is a transmitted NAK signal to the host

in response to the PC host IN or OUT token.

CRCF

R/W

Error condition failure flag include CRC, PID, no integrate token error,

CRCF will be set by hardware and the CRCF need to be cleared by

firmware.

EOT

Token package active flag, low active.

NMI

R/W

NAK token interrupt mask flag. If this bit set, when the device sent a

NAK token to the host, an interrupt will be disabled. Otherwise if this bit

is cleared, when the device sends a NAK token to the host, it will enter

the interrupt sub-routine.

SIES (25H) Register

The MISC register combines command and status to control the desired endpoint FIFO action and to show the status of

the desired endpoint FIFO. MISC will be cleared by a USB reset signal.

Bit No.

Label

R/W

Power-on

Functions

REQUEST

R/W

After setting the status of the desired one, FIFO can be requested by

setting this bit high . After finishing, this bit must be set low.

R/W

To represent the direction and transition end MCU access. When set to

logic 1, the MCU desires to write data to the FIFO. After finishing, this bit

must be set to logic 0 before terminating request to represent transition

end. For an MCU read operation, this bit must be set to logic 0 and set to

logic 1 after finishing.

CLEAR

R/W

MCU requests to clear the FIFO, even if the FIFO is not ready. After

clearing the FIFO, the USB interface will send force_tx_err to tell the

Host that data under-run if the Host wants to read data.

ISO_IN_EN

R/W

Enables the isochronous in pipe interrupt.

ISO_OUT_EN

R/W

Enables the isochronous out pipe interrupt.

SETCMD

R/W

To show that the data in the FIFO is a setup command. This bit will

remain in this state until the next one enters the FIFO.

READY

To show that the desired FIFO is ready

LEN0

To show that the host sent a 0-sized packet to the MCU. This bit must be

cleared by a read action to the corresponding FIFO.

MISC (26H) Register

HT82A834R Datasheet(PDF) 21 Page - Holtek Semiconductor Inc

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