R5F2136CSDFA datasheet(50/61 Pages) RENESAS

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R8C/36T-A Group

4. Electrical Characteristics

R01DS0055EJ0100 Rev.1.00

Page 50 of 58

Dec 09, 2011

Note:

1. 1tCYC = 1/f1 (s)

Table 4.21

Timing Requirements of Clock Synchronous Serial I/O with Chip Select

(during Slave Operation)

(Measurement conditions: Vcc = 1.8 V to 5.5 V, Topr =

20°C to 85°C (N version)/

40°C to 85°C (D version))

Symbol

Parameter

Conditions

Standard

Unit

Min.

Typ.

Max.

tSUCYC

SSCK clock cycle time

4.00

――

tCYC (1)

tHI

SSCK clock high width

0.40

―

0.60

tSUCYC

tLO

SSCK clock low width

0.40

―

0.60

tSUCYC

tRISE

SSCK clock rising time

――

1.00

μs

tFALL

SSCK clock falling time

――

1.00

μs

tSU

SSO data input setup time

10.00

――

SSO data input hold time

2.00

――

tCYC (1)

tLEAD

SCS setup time

1tCYC + 50

――

tLAG

SCS hold time

1tCYC + 50

――

tOD

SSI, SSO data output delay time

4.5 V

 Vcc  5.5 V

――

2.7 V

 Vcc  4.5 V

――

1.8 V

 Vcc  2.7 V

――

100.00

tSA

SSI slave access time

2.7 V

 Vcc  5.5 V

――

1.5tCYC + 100

1.8 V

 Vcc  2.7 V

――

1.5tCYC + 200

tOR

SSI slave out open time

2.7 V

 Vcc  5.5 V

――

1.5tCYC + 100

1.8 V

 Vcc  2.7 V

――

1.5tCYC + 200

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