AD586 datasheet(6/44 Pages) AD

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AD5737

Data Sheet

Rev. B | Page 6 of 44

AC PERFORMANCE CHARACTERISTICS

AVDD = VBOOST_x = 15 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = GNDSWx = 0 V;

REFIN = 5 V; RL = 300 Ω; all specifications TMIN to TMAX, unless otherwise noted.

Table 2.

Parameter1

Min

Typ

Max

Unit

Test Conditions/Comments

DYNAMIC PERFORMANCE, CURRENT

OUTPUT

Output Current Settling Time

µs

To 0.1% FSR, 0 mA to 24 mA range

See Test Conditions/Comments

For settling times when using the dc-to-dc con-

verter, see Figure 25, Figure 26, and Figure 27

Output Noise (0.1 Hz to 10 Hz

Bandwidth)

0.15

LSB p-p

12-bit LSB, 0 mA to 24 mA range

Output Noise Spectral Density

0.5

nA/√Hz

Measured at 10 kHz, midscale output, 0 mA

to 24 mA range

Guaranteed by design and characterization; not production tested.

TIMING CHARACTERISTICS

AVDD = VBOOST_x = 15 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = GNDSWx = 0 V;

REFIN = 5 V; RL = 300 Ω; all specifications TMIN to TMAX, unless otherwise noted.

Table 3.

Parameter1, 2, 3

Limit at TMIN, TMAX

Unit

Description

ns min

SCLK cycle time

ns min

SCLK high time

ns min

SCLK low time

ns min

SYNC falling edge to SCLK falling edge setup time

ns min

24th/32nd SCLK falling edge to SYNC rising edge (see Figure 53)

198

ns min

SYNC high time

ns min

Data setup time

ns min

Data hold time

µs min

SYNC rising edge to LDAC falling edge (all DACs updated or any channel has

digital slew rate control enabled)

µs min

SYNC rising edge to LDAC falling edge (single DAC updated)

t10

ns min

LDAC pulse width low

t11

500

ns max

LDAC falling edge to DAC output response time

t12

See Table 2

µs max

DAC output settling time

t13

ns min

CLEAR high time

t14

µs max

CLEAR activation time

t15

ns max

SCLK rising edge to SDO valid

t16

SYNC rising edge to DAC output response time (LDAC = 0)

µs min

All DACs updated

µs min

Single DAC updated

t17

500

ns min

LDAC falling edge to SYNC rising edge

t18

800

ns min

RESET pulse width

t194

SYNC high to next SYNC low (digital slew rate control enabled)

µs min

All DACs updated

µs min

Single DAC updated

Guaranteed by design and characterization; not production tested.

All input signals are specified with tRISE = tFALL = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.2 V.

See Figure 3, Figure 4, Figure 5, and Figure 6.

This specification applies if LDAC is held low during the write cycle; otherwise, see t9.

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