AD9653 datasheet(28/40 Pages) AD

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AD9653

Data Sheet

Rev. 0 | Page 28 of 40

Figure 72. LVDS Output Timing Example in Reduced Range Mode

An example of the LVDS output using the ANSI-644 standard

(default) data eye and a time interval error (TIE) jitter histo-

gram with trace lengths less than 24 inches on standard FR-4

material is shown in Figure 73.

Figure 73. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths

Less than 24 Inches on Standard FR-4 Material, External 100 Ω Far-End

Termination Only

Figure 74. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths

Greater than 24 Inches on Standard FR-4 Material, External 100 Ω Far-End

Termination Only

Figure 74 shows an example of trace lengths exceeding 24 inches

on standard FR-4 material. Notice that the TIE jitter histogram

reflects the decrease of the data eye opening as the edge deviates

from the ideal position.

It is the user’s responsibility to determine if the waveforms

meet the timing budget of the design when the trace lengths

exceed 24 inches. Additional SPI options allow the user to further

increase the internal termination (increasing the current) of all

four outputs to drive longer trace lengths. This can be achieved

by programming Register 0x15. Even though this produces

sharper rise and fall times on the data edges and is less prone to

bit errors, the power dissipation of the DRVDD supply increases

when this option is used.

The format of the output data is twos complement by default.

An example of the output coding format can be found in Table 12.

To change the output data format to offset binary, see the

Memory Map section.

Data from each ADC is serialized and provided on a separate

channel in two lanes in DDR mode. The data rate for each serial

stream is equal to 16 bits times the sample clock rate, with a

maximum of 500 Mbps/lane [(16 bits × 125 MSPS)/(2 × 2) =

500 Mbps/lane]. The lowest typical conversion rate is 20 MSPS.

See the Memory Map section for details on enabling this feature.

D0 400mV/DIV

D1 400mV/DIV

DCO 400mV/DIV

FCO 400mV/DIV

4ns/DIV

200ps

250ps

300ps

350ps

400ps

450ps

500ps

500

400

300

200

100

–500

–400

–300

–200

–100

–0.8ns

–0.4ns

0ns

0.4ns

0.8ns

EYE: ALL BITS

ULS: 7000/400354

500

400

300

200

100

–500

–400

–300

–200

–100

–0.8ns

–0.4ns

0ns

0.4ns

–0.8ns

EYE: ALL BITS

ULS: 8000/414024

10k

12k

–800ps –600ps

–400ps –200ps

0ps

200ps

400ps

600ps

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