SLx 24C64

Semiconductor Group

21

Preliminary 1998-07-27

31 bytes have to be identical to the bytes stored in ascending address order within the

same page.

A successful verification of each byte is indicated by the EEPROM by pulling the SDA

line to low (acknowledge ACK).

The bit programming procedure is initiated by the STOP condition after verification of the

last byte. Programming is started only if all 256 bits of a page have been verified

successfully. If bit programming has taken place, the address counter points to the

uppermost address of the respective page. The write or erase cycle is finished latest

after 4 ms. Acknowledge polling can be used for speed enhancement in order to detect

the end of the write or erase cycle (refer to chapter 5.3, Acknowledge Polling).

7.3

Protection Bit Read

The byte sequence for random bit read is shown in figure 17.

Figure 17

Byte Sequence for Protection Bit Read

The first command byte CSW followed by the address bytes AHI/ALO determine the

protection bit to be read. The second command byte CSW is followed by the control byte

00

of the addressed page. The other 7 bits are not valid. The page protection status is

indicated as follows:

Protection Bit = 1: A normal write operation changes the data in the associated page

Protection Bit = 0: The data in the associated page are protected against changes.

If the master acknowledges a byte with a low state of the SDA line, the protection bit of

the next page can be read as the first bit of the following byte. If the master releases the

SDA line, a STOP condition has to complete the read procedure. Any number of bytes

with a page protection status at the first bit position can be requested by the master. After

the bit of the uppermost page has been addressed an overflow of the address counter

occurs and the protection bit of the first page will be read next.

0

0

0

000

0 0

C

K

A

C

K

A

...

IED02524

C

K

A

bbb

SS

P

O

P

S

T

S

R

T

A

T

S

R

T

A

T

b = Protection Bit

Bus Activity

SDA Line

EEPROM

Activity

Master

Bus

Byte n

Byte n+1

Command

Data

Control

Data

Byte

CSW

Byte

CTR

Address

EEPROM

Command

CSW

Byte

AHI

Address

EEPROM

ALO

C

K

A

C

K

A

C

K

AA

C

K

A

K

C

0