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LTC2188

2188f

50Ω

100Ω

0.1µF

T1 = MA/COM ETC1-1-13

RESISTORS AND CAPACITORS

ARE 0402 PACKAGE SIZE

50Ω

LTC2188

2188 F12

ENC–

ENC+

0.1µF

Figure 12. Sinusoidal Encode Drive

ENC+

ENC–

PECL OR

LVDS

CLOCK

0.1µF

2188 F13

LTC2188

Figure 13. PECL or LVDS Encode Drive

VDD

LTC2188

2188 F10

ENC–

ENC+

15k

VDD

DIFFERENTIAL

COMPARATOR

30k

Figure 10. Equivalent Encode Input Circuit

for Differential Encode Mode

30k

ENC+

ENC–

2188 F11

1.8V TO 3.3V

LTC2188

CMOS LOGIC

BUFFER

Figure 11. Equivalent Encode Input Circuit

for Single-Ended Encode Mode

mode, ENC– should stay at least 200mV above ground to

avoid falsely triggering the single ended encode mode.

For good jitter performance ENC+ and ENC– should have

fast rise and fall times.

Thesingle-endedencodemodeshouldbeusedwithCMOS

encode inputs. To select this mode, ENC– is connected

to ground and ENC+ is driven with a square wave encode

input. ENC+ can be taken above VDD (up to 3.6V) so 1.8V

to3.3VCMOSlogiclevelscanbeused.TheENC+threshold

is 0.9V. For good jitter performance ENC+ should have fast

rise and fall times.

If the encode signal is turned off or drops below approxi-

mately 500kHz, the A/D enters nap mode.

Clock Duty Cycle Stabilizer

For good performance the encode signal should have a

50% (±10%) duty cycle. If the optional clock duty cycle

stabilizer circuit is enabled, the encode duty cycle can

vary from 10% to 90% and the duty cycle stabilizer will

maintain a constant 50% internal duty cycle. If the encode

signal changes frequency, the duty cycle stabilizer circuit

requires one hundred clock cycles to lock onto the input

clock. The duty cycle stabilizer is enabled by mode control

programming mode).

Forapplicationswherethesamplerateneedstobechanged

quickly, the clock duty cycle stabilizer can be disabled. If

the duty cycle stabilizer is disabled, care should be taken

tomakethesamplingclockhavea50%(±10%)dutycycle.

The duty cycle stabilizer should not be used below 5Msps.

DIGITAL OUTPUTS

Digital Output Modes

The LTC2188 can operate in three digital output modes:

full rate CMOS, double data rate CMOS (to halve the

number of output lines), or double data rate LVDS (to

reduce digital noise in the system.) The output mode

is set by mode control register A3 (serial programming

mode), or by SCK (parallel programming mode). Note that

double data rate CMOS cannot be selected in the parallel

programming mode.

applicaTions inForMaTion

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