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LTC4253/LTC4253A

425353afe

APPLICATIONS INFORMATION

OPERATION

Higher overloads are handled by an analog current limit

loop. If the drop across RS reaches VACL, the current

limiting loop servos the MOSFET gate and maintains a

constant output current of VACL/RS. In current limit mode,

VOUT (MOSFET drain-source voltage drop) typically rises

and this increases MOSFET heating. If VOUT > VDRNCL,

connecting an external resistor, RD between VOUT and

DRAIN allows the fault timing cycle to be shortened by

accelerating the charging of the TIMER capacitor. The

TIMER pull-up current is increased by 8 • IDRN. Note that

because SENSE > 50mV, TIMER charges CT during this

time, and the LTC4253/LTC4253A eventually shut down.

Low impedance failures on the load side of the LTC4253/

LTC4253A, coupled with 48V or more driving potential,

can produce current slew rates well in excess of 50A/μs.

Under these conditions, overshoot is inevitable. A fast

SENSE comparator with a threshold of 200mV detects

overshoot and pulls GATE low much harder and hence

much faster than the weaker current limit loop. The VACL/

RS current limit loop then takes over and servos the cur-

rent as previously described. As before, TIMER runs and

shuts down the LTC4253/LTC4253A when CT reaches 4V.

If CT reaches 4V, the LTC4253/LTC4253A latch off with a

5μA pull-up current source. The LTC4253/LTC4253A circuit

breaker latch is reset by either pulling the RESET pin active

high until TIMER goes low, pulling UV momentarily low,

dropping the input voltage VIN below the internal UVLO

threshold or pulsing TIMER momentarily low with a switch.

Although short-circuits are the most obvious fault type,

several operating conditions may invoke overcurrent

protection. Noise spikes from the backplane or load, input

steps caused by the connection of a second, higher voltage

supply, transient currents caused by faults on adjacent

circuit boards sharing the same power bus or the insertion

of non-hot swappable products could cause higher than

anticipated input current and temporary detection of an

overcurrent condition. The action of TIMER and CT rejects

these events allowing the LTC4253/LTC4253A to “ride out”

temporary overloads and disturbances that could trip a

simple current comparator and, in some cases, blow a fuse.

pins, the area in and around the LTC4253 and all associ-

ated components should be free of any other planes such

as chassis ground, return, or secondary-side power and

ground planes.

VIN may be biased with additional current up to 30mA, to

accomodate external loading such as the PWRGD opto-

couplers shown in Figure 2. As an alternative to running

higher current, simply buffer VIN with an emitter follower

as shown in Figure 3. A method that cascodes the PWRGD

outputs as shown in Figure 17.

VIN is rated to handle 30mA within the thermal limits of

the package, and is tested to survive a 100μs, 100mA

SHUNT REGULATOR

A fast responding shunt regulator clamps the VIN pin to

13V (VZ). Power is derived from –48RTN by an external

current limiting resistor, RIN. A 1μF decoupling capacitor,

CIN filters supply transients and contributes a short delay

at start-up.

To meet creepage requirements RIN may be split into two

or more series connected units. This introduces a wider

total spacing than is possible with a single component

while at the same time ballasting the potential across the

gap under each resistor. The LTC4253 is fundamentally a

low voltage device that operates with –48V as its reference

ground. To further protect against arc discharge into its

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