LT1640AL datasheet(22/34 Pages) LINER

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LTC4253/LTC4253A

425353afe

APPLICATIONS INFORMATION

SENSE RESISTOR CONSIDERATIONS

For proper circuit breaker operation, Kelvin-sense PCB

connections between the sense resistor and the LTC4253/

LTC4253A’s VEE and SENSE pins are strongly recom-

mended. The drawing in Figure 7 illustrates the correct way

of making connections between the LTC4253/LTC4253A

and the sense resistor. PCB layout should be balanced

and symmetrical to minimize wiring errors. In addition,

the PCB layout for the sense resistor should include good

thermal management techniques for optimal sense resistor

power dissipation.

Figure 7. Making PCB Connections to the Sense Resistor

TIMING WAVEFORMS

System Power-Up

Figure 8 details the timing waveforms for a typical power-

up sequence in the case where a board is already installed

in the backplane and system power is applied abruptly. At

time point 1, the supply ramps up, together with UV/OV,

VOUT and DRAIN. VIN and the PWRGD signals follow at

a slower rate as set by the VIN bypass capacitor. At time

point 2, VIN exceeds VLKO and the internal logic checks for

UV > VUVHI (VUV for the LTC4253A), OV < VOVLO (VOV –

VOVHST for the LTC4253A), RESET < 0.8V, GATE < VGATEL,

SENSE < VCB, SS < 20 • VOS, and TIMER < VTMRL. When

all conditions are met, initial timing starts and the TIMER

capacitor is charged by a 5μA current source pull-up. At

time point 3, TIMER reaches the VTMRH threshold and

the initial timing cycle terminates. The TIMER capacitor

is quickly discharged. At time point 4, the VTMRL thresh-

old is reached and the conditions of GATE < VGATEL,

SENSE < VCB and SS < 20 • VOS must be satisfied before

the GATE start-up cycle begins. SS ramps up as dictated

by RSS • CSS (as in Equation 6); GATE is held low by the

analog current limit (ACL) amplifier until SS crosses 20 •

VOS. Upon releasing GATE, 50μA sources into the external

MOSFET gate and compensation network. When the GATE

voltage reaches the MOSFET’s threshold, current flows

into the load capacitor at time point 5. At time point 6,

load current reaches SS control level and the analog cur-

rent limit loop activates. Between time points 6 and 8, the

GATE voltage is servoed, the SENSE voltage is regulated

at VACL(t) (Equation 7) and soft-start limits the slew rate

of the load current. If the SENSE voltage (VSENSE – VEE)

reaches the VCB threshold at time point 7, circuit breaker

TIMER activates. The TIMER capacitor, CT, is charged by

a (200μA + 8 • IDRN) current pull-up. As the load capaci-

tor nears full charge, load current begins to decline. At

time point 8, the load current falls and the SENSE voltage

drops below VACL(t). The analog current limit loop shuts

off and the GATE pin ramps further. At time point 9, the

SENSE voltage drops below VCB, the fault TIMER ends,

followed by a 5μA discharge cycle (cool-off). The duration

between time points 7 and 9 must be shorter than one

circuit breaker delay to avoid fault time-out during GATE

ramp-up. When GATE ramps past the VGATEH threshold

at time point A, PWRGD1 pulls low. At time point B, GATE

reaches its maximum voltage as determined by VIN. At time

point A, SQTIMER starts its ramp-up to 4V. Having satis-

fied the requirement that PWRGD1 is low for more than

one tSQT, PWRGD2 pulls low after EN2 pulls high above

the VIH threshold at time point C. This sets off the second

SQTIMER ramp-up. Having satisfied the requirement that

PWRGD2 is low for more than one tSQT, PWRGD3 pulls

low after EN3 pulls high at time point D.

CURRENT FLOW

FROM LOAD

CURRENT FLOW

TO –48V BACKPLANE

SENSE RESISTOR

TRACK WIDTH W:

0.03" PER AMP

ON 1 OZ COPPER

SENSE

VEE

4253 F07

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