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EDJ8232E5MB Datasheet(PDF) 3 Page - Elpida Memory |
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EDJ8232E5MB Datasheet(HTML) 3 Page - Elpida Memory |
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3 / 142 page  EDJ8232E5MB Data Sheet E1813E40 (Ver. 4.0) 3 Pin Configurations /xxx indicates active low signal. A B C D E F G H J K L M N P T R 12 3 10 11 9 (Top view) 136-ball FBGA VSS A13 A14 A8 VREFDQ /DQS0 DQ1 VDD VSSQ VDDQ A3 A5 BA2 A0 A2 A12(/BC) VREFCA A4 VSS /WE A7 A9 A11 A6 A10(AP) U 412 DQ9 VSSQ VSS VDD DQ0 VSSQ DQ3 DQ11 VSSQ DQ8 VDDQ VSSQ DQ2 VSSQ /DQS1 DQS1 VDDQ DM0 DM1 VSSQ DQ10 VDDQ VDDQ DQS0 VSSQ VDDQ VSSQ DQ4 VDDQ DQ5 DQ13 VDDQ DQ12 VSSQ VSS DQ6 VDDQ DQ7 DQ15 VDDQ DQ14 VSS /RAS VDD /CAS NC VDD CK CKE /CK /RESET ODT /CS NC NC ZQ0 A1 ZQ1 VSS BA0 BA1 VDD VDD VSS DQ24 VDDQ DQ25 DQ17 VDDQ DQ16 VSS VSSQ DQ26 VDDQ DQ27 DQ19 VDDQ DQ18 VSSQ /DQS3 VSSQ /DQS2 DQS2 VDDQ DQS3 VSSQ VDDQ DQ28 VSSQ VDDQ DM3 DM2 VSSQ DQ20 VDDQ VDDQ DQ30 VSSQ DQ29 DQ21 VSSQ DQ22 VDDQ DQ31 VDD VSSQ VSS DQ23 VSSQ VSS VDD Pin name Function Pin name Function A0 to A14* 2 Address inputs A10(AP): Auto precharge A12(/BC): Burst chop /RESET* 2 Active low asynchronous reset BA0 to BA2* 2 Bank select VDD Supply voltage for internal circuit DQ0 to DQ31 Data input/output VSS Ground for internal circuit DQS0 to DQS3, /DQS0 to /DQS3 Differential data strobe VDDQ Supply voltage for DQ circuit /CS* 2 Chip select VSSQ Ground for DQ circuit /RAS, /CAS, /WE* 2 Command input VREFDQ Reference voltage for DQ CKE* 2 Clock enable VREFCA Reference voltage CK, /CK Differential clock input ZQ0, ZQ1 Reference pin for ZQ calibration DM0 to DM3 Write data mask NC* 1 No connection ODT* 2 ODT control Notes: 1. Not internally connected with die. 2. Input only pins (address, command, CKE, ODT and /RESET) do not supply termination. |
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