MPC8378E datasheet(32/128 Pages) FREESCALE

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MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8

Freescale Semiconductor

This figure provides the AC test load for eTSEC.

Figure 12. eTSEC AC Test Load

This figure shows the MII receive AC timing diagram.

Figure 13. MII Receive AC Timing Diagram

8.3.4

RGMII and RTBI AC Timing Specifications

This table presents the RGMII and RTBI AC timing specifications.

RX_CLK clock rise time (20%–80%)

tMRXR

1.0

—

4.0

RX_CLK clock fall time (80%–20%)

tMRXF

1.0

—

4.0

Note:

1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)

(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH

symbolizes MII receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the

tMRX clock reference (K) going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with

respect to the time data input signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state

or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock

of a particular functional. For example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times,

the latter convention is used with the appropriate letter: R (rise) or F (fall).

Table 33. RGMII and RTBI AC Timing Specifications

At recommended operating conditions with LVDD of 2.5 V ± 5%.

Parameter

Symbol1

Min

Typical

Max

Unit

Note

Data to clock output skew (at transmitter)

tSKRGT

–600

600

—

Data to clock input skew (at receiver)

tSKRGT

1.0

—

2.8

Clock period

tRGT

7.2

8.0

8.8

Table 32. MII Receive AC Timing Specifications (continued)

At recommended operating conditions with LVDD of 3.3 V ± 5%.

Parameter

Symbol1

Min

Typical

Max

Unit

Output

Z0 = 50 Ω

LVDD/2

RL = 50 Ω

RX_CLK

RXD[3:0]

tMRDXKL

tMRX

tMRXH

tMRXR

tMRXF

RX_DV

RX_ER

tMRDVKH

Valid Data

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