AD9518-3ABCPZ datasheet(27/64 Pages) AD

27 / 64 page

Data Sheet

AD9518-3

Rev. B | Page 27 of 64

Charge Pump (CP)

The charge pump is controlled by the PFD. The PFD monitors

the phase and frequency relationship between its two inputs, and

tells the CP to pump up or pump down to charge or discharge the

integrating node (part of the loop filter). The integrated and

filtered CP current is transformed into a voltage that drives the

tuning node of the internal VCO through the LF pin (or the tuning

pin of an external VCO) to move the VCO frequency up or down.

The CP can be set (Register 0x010[6:4]) for high impedance

(allows holdover operation), for normal operation (attempts to

lock the PLL loop), for pump up, or for pump down (test modes).

The CP current is programmable in eight steps from (nominally)

600 μA to 4.8 mA. The exact value of the CP current LSB is set

by the CPRSET resistor, which is nominally 5.1 kΩ. If the value

of the resistor connected to the CP_RSET pin is doubled, the

resulting charge pump current range becomes 300 μA to 2.4 mA.

On-Chip VCO

The AD9518 includes an on-chip VCO that covers the frequency

range shown in Table 2. The calibration procedure ensures that

the VCO operating voltage is centered for the desired VCO

frequency. The VCO must be calibrated when the VCO loop

is first set up, as well as any time the nominal VCO frequency

changes. However, once the VCO is calibrated, the VCO has

sufficient operating range to stay locked over temperature and

voltage extremes without needing additional calibration. See the

VCO Calibration section for more information.

The on-chip VCO is powered by an on-chip, low dropout (LDO),

linear voltage regulator. The LDO provides some isolation of

the VCO from variations in the power supply voltage level. The

BYPASS pin should be connected to ground by a 220 nF

capacitor to ensure stability. This LDO employs the same

technology used in the anyCAP® line of regulators from Analog

Devices, Inc., making it insensitive to the type of capacitor used.

Driving an external load from the BYPASS pin is not supported.

Note that the reference input signal must be present and the

VCO divider must not be static during VCO calibration.

PLL External Loop Filter

When using the internal VCO, the external loop filter should

be referenced to the BYPASS pin for optimal noise and spurious

performance. An example of an external loop filter for a PLL

that uses the internal VCO is shown in Figure 32. The third-

order design that is shown in Figure 32 usually offers the best

performance. A loop filter must be calculated for each desired

PLL configuration. The values of the components depend upon the

VCO frequency, the KVCO, the PFD frequency, the CP current, the

desired loop bandwidth, and the desired phase margin. The loop

filter affects the phase noise, loop settling time, and loop stability.

A basic knowledge of PLL theory is helpful for understanding

loop filter design. ADIsimCLK can help with the calculation

of a loop filter according to the application requirements.

VCO

CHARGE

PUMP

BYPASS

31pF

CBP = 220nF

AD9518-3

Figure 32. Example of External Loop Filter for a PLL Using the Internal VCO

When using an external VCO, the external loop filter should be

referenced to ground. See Figure 33 for an example of an external

loop filter for a PLL using an external VCO. For more information

on suggested loop filters, see the UG-075 User Guide.

CLK/CLK

EXTERNAL

VCO/VCXO

CHARGE

PUMP

AD9518-3

Figure 33. Example of External Loop Filter for a PLL Using an External VCO

PLL Reference Inputs

The AD9518 features a flexible PLL reference input circuit that

allows either a fully differential input or two separate single-ended

inputs. The input frequency range for the reference inputs is

specified in Table 2. Both the differential and the single-ended

inputs are self-biased, allowing for easy ac coupling of input signals.

The differential input and the single-ended inputs share the

two pins, REFIN and REFIN (REF1 and REF2, respectively). The

desired reference input type is selected and controlled by

and

Table 42

Table 44

When the differential reference input is selected, the self-bias

level of the two sides is offset slightly (~100 mV, see Table 2) to

prevent chattering of the input buffer when the reference is slow

or missing. This increases the voltage swing that is required of the

driver and overcomes the offset. The differential reference input

can be driven by either ac-coupled LVDS or ac-coupled LVPECL

signals.

The single-ended inputs can be driven by either a dc-coupled

CMOS level signal or an ac-coupled sine-wave or square wave.

Each single-ended input can be independently powered down

when not needed to increase isolation and reduce power. Either

a differential or a single-ended reference must be specifically

enabled. All PLL reference inputs are off by default.

The differential reference input is powered down whenever the

PLL is powered down, or when the differential reference input

is not selected. The single-ended buffers power down when the

PLL is powered down, and when their individual power down

registers are set. When the differential mode is selected, the

single-ended inputs are powered down.

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