DAC1282IPW datasheet(26/43 Pages) TI1

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CLK

DVDD

Status

1.3 V nom

AVDD - AVSS

1.4 V nom

2 t

CLK

Operational

Reset

DAC1282

SBAS490

– DECEMBER 2011

www.ti.com

At power-on, when the latter of DVDD exceeds approximately 1.3 V, or the difference of AVDD

– AVSS exceeds

approximately 1.4 V, an internal power-on reset (POR) occurs. During POR, the device is held in a reset

condition for a period of 216 fCLK periods as shown in Figure 43. During this time, the DAC1282 output is held at 0

V, differential. SPI communications are not possible during this time. After the reset time elapses, the default

settings are loaded: 31.25 Hz, 28 mVRMS amplitude, and output switch off. SPI communications can then be

started.

Figure 43. Power-On Sequence

Power Consumption

The power consumed by the DAC1282 depends on the analog gain. Table 13 shows the DAC power

consumption.

Table 13. Power Consumption

ANALOG GAIN

POWER (mW)(1)

1/1

1/2

1/4

1/8

1/16

1/32

1/64

(1)

Typical power consumption with VREF = 5 V and VOUT = 0 V. Excludes pulse mode.

Offset and Gain Error

The DAC1282 features a low offset error (

±7/Gain + 50 ppm FS typical) and low gain error (0.1 % typical). Offset

and gain drift are also very low for the DAC1282. Drift is calculated using the box calculation method of

Equation 4:

Drift Calculation = (Max

– Min)/Temperature Range (ppm/°C)

Where:

Max and Min are, respectively, the maximum and minimum offset and gain errors (in ppm) recorded over the

specified temperature range of

–40°C to +85°C.

(4)

Gain match is the gain error of Gain = 1/1 relative to all analog gains.

Signal-to-Noise Ratio (SNR)

The DAC1282 achieves excellent signal-to-noise ratio (SNR) performance. The SNR data are obtained using the

DAC circuit of Figure 50 and data captured by the ADS1282.

SNR is measured with a signal level of

–0.5 dBFS and a 31.25-Hz test frequency, then taking the fast fourier

transform (FFT) of 4096 data points from the ADS1282, using complementing gains. The noise power is

calculated over the bandwidth of 413 Hz (1-ms sample period). The dc, fundamental, and harmonic bins are

removed to calculate the SNR. The SNR measurement represents the combination of the ADS1282 SNR and the

SNR of the DAC1282.

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