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CLVTH16374IDLREP Datasheet(PDF) 1 Page - Texas Instruments

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Part # CLVTH16374IDLREP
Description  3.3-V ABT 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
PDF  10 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CLVTH16374IDLREP Datasheet(HTML) 1 Page - Texas Instruments

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SN74LVTH16374EP
3.3V ABT 16BIT EDGETRIGGERED DTYPE FLIPFLOP
WITH 3STATE OUTPUTS
SCBS779A − NOVEMBER 2003 – OCTOBER 2004
1
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
D Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D Enhanced Diminishing Manufacturing
Sources (DMS) Support
D Enhanced Product-Change Notification
D Qualification Pedigree†
D Member of the Texas Instruments
Widebus
 Family
D State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation
D Supports Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
3.3-V VCC)
D Supports Unregulated Battery Operation
Down to 2.7 V
D Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
D Ioff and Power-Up 3-State Support Hot
Insertion
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
† Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
D Flow-Through Architecture Optimizes PCB
Layout
D Latch-Up Performance Exceeds 500 mA Per
JESD 17
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
description/ordering information
The SN74LVTH16374 is a 16-bit edge-triggered D-type flip-flop with 3-state outputs designed for low-voltage
(3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. This
device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working
registers.
This device can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK),
the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs.
Copyright
 2004, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Widebus is a trademark of Texas Instruments.
DGG OR DL PACKAGE
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1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
1CLK
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2CLK
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.


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