THS8200IPFPEP datasheet(13/104 Pages) TI1

Part #	THS8200IPFPEP

Description	All-Format Oversampled Component Video/PC Graphics D/A System With Three 11-Bit DACs, CGMS Data Insertion

PDF	104 Pages

Scroll/Zoom	100%

Manufacturer	TI1 [Texas Instruments]

Direct Link	http://www.ti.com

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13 / 104 page

THS8200-EP

www.ti.com

SLES253 – DECEMBER 2009

TERMINAL FUNCTIONS (continued)

TERMINAL

I/O(1)

DESCRIPTION

NAME

NO.

Serial clock line of I2C bus interface. Open-collector. Maximum specified clock speed is

SCL

400 kHz (fast I2C).

SDA

Serial data line of I2C bus interface. Open-collector.

VDD_DLL

PWR

Power supply of clock doubler, nominal 1.8 V

VDD_IO

19, 46, 70

PWR

I/O ring power, 1.8 V or 3.3 V nominal

Vertical source synchronization. In slave timing mode, this is an input from the video data

VS_IN

I/O

source. In master timing mode, this is an output to the video data source with programmable

timing and polarity, serving as a vertical data qualification signal to the video source.

Vertical sync output (to display). Irrespective of slave/master timing mode configuration, this

VS_OUT

is always an output with timing generated by the DTG.

Overview

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Product Folder Link(s): THS8200-EP

THS8200IPFPEP Datasheet(PDF) 13 Page - Texas Instruments