TMS570LS3135 datasheet(6/154 Pages) TI1

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TMS570LS2125

TMS570LS2135

TMS570LS3135

SPNS164

– SEPTEMBER 2011

www.ti.com

TMS570LSxxx5 16/32-Bit RISC Flash

4.6

Clocks

.............................................. 57

Microcontroller

.......................................... 1

4.7

Clock Monitoring

.................................... 65

1.1

Features

.............................................. 1

4.8

Glitch Filters

........................................ 67

1.2

Applications

.......................................... 2

4.9

Device Memory Map

................................ 68

4.10

Flash Memory

...................................... 75

1.3

Description

........................................... 3

4.11

Tightly-Coupled RAM Interface Module

............ 78

1.4

Functional Block Diagram

............................ 5

4.12

Parity Protection for Accesses to peripheral RAMs

1.1

Device Configuration

................................. 7

...................................................... 78

Device Package and Terminal Functions

......... 11

4.13

On-Chip SRAM Initialization and Testing

........... 80

2.2

PGE QFP Package Pinout (144-Pin)

............... 11

4.14

External Memory Interface (EMIF)

................. 82

2.3

ZWT BGA Package Ball-Map (337 Ball Grid Array)

4.15

Vectored Interrupt Manager

........................ 89

...................................................... 12

4.16

DMA Controller

..................................... 92

2.4

Terminal Functions

................................. 13

4.17

Real Time Interrupt Module

........................ 94

Device Operating Conditions

....................... 40

4.18

Error Signaling Module

............................. 96

3.1

Absolute Maximum Ratings Over Operating

4.19

Reset / Abort / Error Sources

..................... 100

Free-Air Temperature Range,

...................... 40

4.20

Digital Windowed Watchdog

...................... 102

3.2

Device Recommended Operating Conditions

...... 40

4.21

Debug Subsystem

................................. 103

3.3

Switching Characteristics over Recommended

Peripheral Information and Electrical

Operating Conditions for Clock Domains

........... 41

Specifications

......................................... 114

3.4

Wait States Required

............................... 41

5.1

Peripheral Legend

................................. 114

3.5

Power Consumption Over Recommended

5.2

Multi-Buffered 12bit Analog-to-Digital Converter

Operating Conditions

............................... 42

..................................................... 114

3.6

Input/Output Electrical Characteristics Over

5.3

General-Purpose Input/Output

.................... 125

Recommended Operating Conditions

.............. 43

5.4

Enhanced High-End Timer (N2HET)

.............. 126

3.7

Output Buffer Drive Strengths

...................... 43

5.5

FlexRay Interface

................................. 130

3.8

Input Timings

....................................... 44

5.6

Controller Area Network (DCAN)

.................. 132

3.9

Output Timings

..................................... 45

5.7

Local Interconnect Network Interface (LIN)

....... 133

3.10

Low-EMI Output Buffers

............................ 47

5.8

Serial Communication Interface (SCI)

............ 134

System Information and Electrical Specifications

5.9

Inter-Integrated Circuit (I2C)

...................... 135

............................................................. 49

5.10

Multi-Buffered / Standard Serial Peripheral Interface

..................................................... 138

4.1

Device Power Domains

............................. 49

Mechanical Data

...................................... 150

4.2

Voltage Monitor Characteristics

.................... 50

6.1

Thermal Data

...................................... 150

4.3

Power Sequencing and Power On Reset

.......... 51

6.2

Packaging Information

............................ 150

4.4

Warm Reset (nRST)

................................ 53

4.5

™ CPU Information

............. 54

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