SN74ACT2440FN datasheet(10/33 Pages) TI1

10 / 33 page

SN74ACT2440

NuBus

™ INTERFACE CONTROLLER

SCHS010 – D3158, OCTOBER 1988 – REVISED JANUARY 1991

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Table 2. Master Block-Transfer Function Table

LOCTM1

LOCTM0

BLOCK

SIZE

TYPE OF

CYCLE

Write

Read

slave block-transfer cycles

The ’ACT2440 can support slave block-transfer cycles with the addition of the ’ALS2442. The first responsibility

of a slave during block transfers is to determine the type and size of the block transfer. This information is

provided by the requesting master and must be decoded from the TMx lines and the A5–A0 address lines (as

provided by the ’ACT2420s). See Table 3 for additional details.

The slave interim acknowledge input (SIACK) generates the interim acknowledge cycles via TM0. The slave

external request output (SEREQ) signals the local board when an interim acknowledge has occurred on the bus.

Figure 14 shows the timing diagram of a typical slave block read. Figure 15 shows the timing diagram of a typical

slave block write. The beginning of these cycles looks like any other slave cycle; SEREQ goes active (low),

signaling the local board that another master is requesting the local board. On the first sample edge after SGNTA

is taken active (low), the AEN buffer signal is driven low, enabling the NuBus

™ addresses onto the local board.

The A0, A1, and TMx lines must be decoded as provided on the ’ALS2442 in order to generate a block-transfer

signal (represented on the timing diagrams as BLOCK). When this signal goes active (high), it signals the local

board that a block transfer has been requested. Decoding A5-A2 determines the number of words to be

transferred. The final acknowledge cycle is generated by driving LACK low.

Table 3. Slave Block-Transfer Decode Table

NTM1