SST49LF004A datasheet(9/36 Pages) SST

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Advance Information

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

S71161-06-000

9/01

504

Sector-Erase Operation

The Sector-Erase operation allows the system to erase the

device on a sector-by-sector basis. The sector architecture

is based on uniform sector size of 4 KByte. The Sector-

Erase operation is initiated by executing a six-byte com-

mand load sequence for Software Data Protection with

Sector-Erase command (30H) and sector address (SA) in

the last bus cycle. The internal Erase operation begins after

the sixth WE# pulse. The End-of-Erase can be determined

using either Data# Polling or Toggle Bit methods. See Fig-

ure 19 for Sector-Erase timing waveforms. Any commands

written during the Sector-Erase operation will be ignored.

Block-Erase Operation

The Block-Erase Operation allows the system to erase

the device in 64 KByte uniform block size for the

SST49LF003A/SST49LF004A/SST49LF008A and 16

KByte uniform block size for the SST49LF002A. The

Block-Erase operation is initiated by executing a six-byte

command load sequence for Software Data Protection

with Block-Erase command (50H) and block address.

The internal Block-Erase operation begins after the sixth

WE# pulse. The End-of-Erase can be determined using

either Data# Polling or Toggle Bit methods. See Figure

20 for timing waveforms. Any commands written during

the Block-Erase operation will be ignored.

Chip-Erase

The SST49LF00xA device provides a Chip-Erase opera-

tion only in PP Mode, which allows the user to erase the

entire memory array to the ‘1’s state. This is useful when

the entire device must be quickly erased.

The Chip-Erase operation is initiated by executing a six-

byte Software Data Protection command sequence with

Chip-Erase command (10H) with address 5555H in the last

byte sequence. The internal Erase operation begins with

the rising edge of the sixth WE#. During the internal Erase

operation, the only valid read is Toggle Bit or Data# Polling.

See Table 10 for the command sequence, Figure 21 for

timing diagram, and Figure 29 for the flowchart. Any com-

mands written during the Chip-Erase operation will be

ignored.

Write Operation Status Detection

The SST49LF00xA device provides two software means

to detect the completion of a Write (Program or Erase)

cycle, in order to optimize the system write cycle time. The

software detection includes two status bits: Data# Polling

(DQ7) and Toggle Bit (DQ6). The End-of-Write detection

mode is enabled after the rising edge of WE# which ini-

tiates the internal Program or Erase operation.

The actual completion of the nonvolatile write is asynchro-

nous with the system; therefore, either a Data# Polling or Tog-

gle Bit read may be simultaneous with the completion of the

Write cycle. If this occurs, the system may possibly get an

erroneous result, i.e., valid data may appear to conflict with

either DQ7 or DQ6. In order to prevent spurious rejection, if an

erroneous result occurs, the software routine should include a

loop to read the accessed location an additional two (2) times.

If both reads are valid, then the device has completed the

Write cycle, otherwise the rejection is valid.

Data# Polling (DQ7)

When the SST49LF00xA device is in the internal Program

operation, any attempt to read DQ7 will produce the com-

plement of the true data. Once the Program operation is

completed, DQ7 will produce true data. Note that even

though DQ7 may have valid data immediately following the

completion of an internal Write operation, the remaining

data outputs may still be invalid: valid data on the entire

data bus will appear in subsequent successive Read

cycles after an interval of 1 µs. During internal Erase opera-

tion, any attempt to read DQ7 will produce a ‘0’. Once the

internal Erase operation is completed, DQ7 will produce a

‘1’. The Data# Polling is valid after the rising edge of fourth

WE# pulse for Program operation. For Sector- or Chip-

Erase, the Data# Polling is valid after the rising edge of

sixth WE# pulse. See Figure 16 for Data# Polling timing

diagram and Figure 27 for a flowchart. Proper status will

not be given using Data# Polling if the address is in the

invalid range.

Toggle Bit (DQ6)

During the internal Program or Erase operation, any con-

secutive attempts to read DQ6 will produce alternating ‘0’s

and ‘1’s, i.e., toggling between 0 and 1. When the internal

Program or Erase operation is completed, the toggling will

stop. The device is then ready for the next operation. The

Toggle Bit is valid after the rising edge of fourth WE# pulse

for Program operation. For Sector-, Block- or Chip-Erase,

the Toggle Bit is valid after the rising edge of sixth WE#

pulse. See Figure 17 for Toggle Bit timing diagram and Fig-

ure 27 for a flowchart.

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