SST49LF004A datasheet(10/36 Pages) SST

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Advance Information

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

S71161-06-000

9/01

504

Data Protection

The SST49LF00xA device provides both hardware and

software features to protect nonvolatile data from inadvert-

ent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# pulse of less than 5 ns will

not initiate a Write cycle.

VDD Power Up/Down Detection: The Write operation is

inhibited when VDD is less than 1.5V.

Write Inhibit Mode: Forcing OE# low, WE# high will inhibit

the Write operation. This prevents inadvertent writes during

power-up or power-down.

Software Data Protection (SDP)

The SST49LF00xA provides the JEDEC approved Soft-

ware Data Protection scheme for all data alteration opera-

tion, i.e., program and erase. Any Program operation

requires the inclusion of a series of three byte sequence.

The three byte-load sequence is used to initiate the Pro-

gram operation, providing optimal protection from inadvert-

ent Write operations, e.g., during the system power-up or

power-down. Any Erase operation requires the inclusion of

six byte load sequence. The SST49LF00xA device is

shipped with the Software Data Protection permanently

enabled. See Table 10 for the specific software command

codes. During SDP command sequence, invalid com-

mands will abort the device to read mode, within TRC.

Electrical Specifications

The AC and DC specifications for the FWH Interface sig-

nals (FWH[3:0], CLK, FWH4, and RST#) as defined in

Section 4.2.2 of the PCI Local Bus Specification, Rev. 2.1.

Refer to Table 11 for the DC voltage and current specifica-

tions. Refer to the tables on pages 20 through 24 for the AC

timing specifications for Clock, Read/Write, and Reset

operations.

Product Identification

The product identification mode identifies the device as the

SST49LF00xA and manufacturer as SST.

Design Considerations

SST recommends a high frequency 0.1 µF ceramic capacitor

to be placed as close as possible between VDD and VSS less

than 1 cm away from the VDD pin of the device. Additionally, a

low frequency 4.7 µF electrolytic capacitor from VDD to VSS

should be placed within 1 cm of the VDD pin. If you use a

socket for programming purposes add an additional 1-10 µF

next to each socket.

The RST# pin must remain stable at VIH for the entire dura-

tion of an Erase operation. WP# must remain stable at VIH for

the entire duration of the Erase and Program operations for

non-Boot Block sectors. To write data to the top Boot Block

sectors, the TBL# pin must also remain stable at VIH for the

entire duration of the Erase and Program operations.

TABLE

7: PRODUCT IDENTIFICATION

Byte

Data

JEDEC ID

Address

Location

Manufacturer’s ID

0000H

BFH

FFBC0000H

Device ID

SST49LF002A

0001H

57H

FFBC0001H

SST49LF003A

0001H

1BH

FFBC0001H

SST49LF004A

0001H

60H

FFBC0001H

SST49LF008A

0001H

5AH

FFBC0001H

T7.5 504

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