TPS709xx

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SBVS186 – MARCH 2012

THERMAL INFORMATION

Thermal protection disables the output when the junction temperature rises to approximately +165°C, allowing

the device to cool. When the junction temperature cools to approximately +145°C, the output circuitry is again

enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection

circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a

result of overheating.

Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate

heatsink. For reliable operation, junction temperature should be limited to +125°C, maximum. To estimate the

margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal

protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should

trigger at least +35°C above the maximum expected ambient condition of the particular application. This

configuration produces a worst-case junction temperature of +125°C at the highest expected ambient

temperature and worst-case load.

The TPS709xx internal protection circuitry is designed to protect against overload conditions. It is not intended to

replace proper heatsinking. Continuously running the TPS709xx into thermal shutdown degrades device

reliability.

POWER DISSIPATION

The ability to remove heat from the die is different for each package type, which presents different considerations

in the printed circuit board (PCB) layout. The PCB area around the device that is free of other components

moves the heat from the device to ambient air. Performance data for JEDEC low and high-K boards are given in

the Thermal Information table. Using heavier copper increases the effectiveness in removing heat from the

device. The addition of plated through-holes to heat-dissipating layers also improves the heatsink effectiveness.

the output current and the voltage drop across the output pass element, as shown in Equation 1:

(1)

Copyright © 2012, Texas Instruments Incorporated

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