TDA7562B

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Doc ID 17984 Rev 2

5

Data transmission from microprocessor to the TDA7562B and voice-overs takes place

resistors to positive supply voltage must be connected).

5.1

Data validity

As shown by Figure 25, the data on the SDA line must be stable during the high period of

the clock.

The high and low state of the data line can only change when the clock signal on the SCL

line is low.

5.2

Start and stop conditions

As shown by Figure 26 a start condition is a high to low transition of the SDA line while SCL

is high.

The stop condition is a low to high transition of the SDA line while SCL is high.

5.3

Byte format

Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an

acknowledge bit. The MSB is transferred first.

5.4

Acknowledge

The transmitter* puts a resistive high level on the SDA line during the acknowledge clock

pulse (see Figure 27). The receiver** the acknowledges has to pull-down (LOW) the SDA

line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock

pulse.

* Transmitter

–

master (µP) when it writes an address to the TDA7562B

–

slave (TDA7562B) when the µP reads a data byte from TDA7562B

** Receiver

–

slave (TDA7562B) when the µP writes an address to the TDA7562B

–

master (µP) when it reads a data byte from TDA7562B

Figure 25.