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ST10F276E Datasheet(PDF) 138 Page - STMicroelectronics |
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ST10F276E Datasheet(HTML) 138 Page - STMicroelectronics |
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138 / 235 page  Register set ST10F276E 138/235 Doc ID 12303 Rev 3 22.3 General purpose registers (GPRs) The GPRs form the register bank that the CPU works with. This register bank may be located anywhere within the internal RAM via the Context Pointer (CP). Due to the addressing mechanism, GPR banks reside only within the internal RAM. All GPRs are bit- addressable. The first eight GPRs (R7...R0) may also be accessed bytewise. Other than with SFRs, writing to a GPR byte does not affect the other byte of the respective GPR. The respective halves of the byte-accessible registers have special names: hwbit Bit that is set/cleared by hardware is written in bold Table 65. General purpose registers (GPRs) Name Physical address 8-bit address Description Reset value R0 (CP) + 0 F0h CPU general purpose (word) register R0 UUUUh R1 (CP) + 2 F1h CPU general purpose (word) register R1 UUUUh R2 (CP) + 4 F2h CPU general purpose (word) register R2 UUUUh R3 (CP) + 6 F3h CPU general purpose (word) register R3 UUUUh R4 (CP) + 8 F4h CPU general purpose (word) register R4 UUUUh R5 (CP) + 10 F5h CPU general purpose (word) register R5 UUUUh R6 (CP) + 12 F6h CPU general purpose (word) register R6 UUUUh R7 (CP) + 14 F7h CPU general purpose (word) register R7 UUUUh R8 (CP) + 16 F8h CPU general purpose (word) register R8 UUUUh R9 (CP) + 18 F9h CPU general purpose (word) register R9 UUUUh R10 (CP) + 20 FAh CPU general purpose (word) register R10 UUUUh R11 (CP) + 22 FBh CPU general purpose (word) register R11 UUUUh R12 (CP) + 24 FCh CPU general purpose (word) register R12 UUUUh R13 (CP) + 26 FDh CPU general purpose (word) register R13 UUUUh R14 (CP) + 28 FEh CPU general purpose (word) register R14 UUUUh R15 (CP) + 30 FFh CPU general purpose (word) register R15 UUUUh Table 66. General purpose registers (GPRs) bytewise addressing Name Physical address 8-bit address Description Reset value RL0 (CP) + 0 F0h CPU general purpose (byte) register RL0 UUh RH0 (CP) + 1 F1h CPU general purpose (byte) register RH0 UUh RL1 (CP) + 2 F2h CPU general purpose (byte) register RL1 UUh RH1 (CP) + 3 F3h CPU general purpose (byte) register RH1 UUh |
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